Dumb VHDL Question -- Type Conversion
in [FPGA]
|
From: Tim Wescott on 16 Jul 2010 15:07 How do I assign an integer value to 'signed' or 'unsigned' from the IEEE libraries? I'm having this difficulty with my test benches. Surely there's a set of library functions to do it, but I can't seem to figure out what they are!! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
From: Rob Gaddi on 16 Jul 2010 15:18 On 7/16/2010 12:07 PM, Tim Wescott wrote: > How do I assign an integer value to 'signed' or 'unsigned' from the IEEE > libraries? > > I'm having this difficulty with my test benches. Surely there's a set of > library functions to do it, but I can't seem to figure out what they are!! > I'm assuming you're talking about numeric_std? TO_SIGNED(intval, width) and TO_UNSIGNED(intval, width) -- Rob Gaddi, Highland Technology Email address is currently out of order
From: Tim Wescott on 16 Jul 2010 17:06 On 07/16/2010 12:18 PM, Rob Gaddi wrote: > On 7/16/2010 12:07 PM, Tim Wescott wrote: >> How do I assign an integer value to 'signed' or 'unsigned' from the IEEE >> libraries? >> >> I'm having this difficulty with my test benches. Surely there's a set of >> library functions to do it, but I can't seem to figure out what they >> are!! >> > > I'm assuming you're talking about numeric_std? > > TO_SIGNED(intval, width) and TO_UNSIGNED(intval, width) > That worked. I seem to have a collision between libraries in my Xilinx ISE: declaring both of the following: USE ieee.numeric_std.ALL; use IEEE.STD_LOGIC_ARITH.ALL; gets me a flood of errors, although I seem to be able to comment out the std_logic_arith. I lack a good language/library reference*, or I'm stupidly not looking in the right place, else I'd be able to answer my questions by myself. * By definition -- because a good reference would answer the question. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
From: MM on 16 Jul 2010 17:24 "Tim Wescott" <tim(a)seemywebsite.com> wrote in message news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d(a)web-ster.com... > I seem to have a collision between libraries in my Xilinx ISE: > > declaring both of the following: > > USE ieee.numeric_std.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > > gets me a flood of errors, although I seem to be able to comment out the > std_logic_arith. > These two libs should never be used together. The former is a standard library, which should be used in new code, and the latter is a legacy Synopsys library which might be required when working with the existing code. /Mikhail
From: Tim Wescott on 16 Jul 2010 18:01 On 07/16/2010 02:24 PM, MM wrote: > "Tim Wescott"<tim(a)seemywebsite.com> wrote in message > news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d(a)web-ster.com... >> I seem to have a collision between libraries in my Xilinx ISE: >> >> declaring both of the following: >> >> USE ieee.numeric_std.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> >> gets me a flood of errors, although I seem to be able to comment out the >> std_logic_arith. >> > > These two libs should never be used together. The former is a standard > library, which should be used in new code, and the latter is a legacy > Synopsys library which might be required when working with the existing > code. Ah, Xilinx -- the latter is what Xilinx sticks in as boilerplate when you get lazy and tell it to just make you a test bench from a file. Thanks for the tip. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
|
Next
|
Last
Pages: 1 2 3 Prev: Drigmorn4 - Spartan-6 Board Next: Cortex-M1 in Actel in strait VHDL? |