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From: mmcshmi11 on 23 Nov 2009 12:52
I'm working with a xilinx virtex 5 board (with the VLX110T) and have been
trying to get any kind of output to a DVI monitor. I'm using the IIC core
in XPS to try and program the CH7301. I'm using a clock generator to send a
25MHz clock to the xclk pin, sending a high value to the xclk*, and not
sending any of the 12 data bits because I'm assuming they aren't needed for
color bars...

I can talk to the CH7301 over the I2C bus and I'm not sure if I am
programming the control registers wrong or possibly my code is written
wrong and not programming them at all. Can anybody help me with this? The
code is below:

#define write_CH7301 0xEC //device address 0x76 shifted left 1 bit

/* Register Declarations */
#define GIE (*((volatile unsigned long*)(XPAR_IIC_BASEADDR + 0x01C)))
#define ISR (*((volatile unsigned long*)(XPAR_IIC_BASEADDR + 0x020)))
#define IER (*((volatile unsigned long*)(XPAR_IIC_BASEADDR + 0x028)))
#define SOFTR (*((volatile unsigned long*)(XPAR_IIC_BASEADDR + 0x040)))
#define CR (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x100)))
#define SR (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x104)))
#define TX_FIFO (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x108)))
#define RC_FIFO (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x10C)))
#define ADR (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x110)))
#define TX_FIFO_OCY (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x114)))
#define RC_FIFO_OCY (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x118)))
#define TEN_ADR (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x11C)))
#define RC_FIFO_PIRQ (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x120)))
#define GPO (*((volatile unsigned long*)(XPAR_IIC_BASEADDR +
0x124)))

void init_CH7301()
{
GIE = 0x80000000; //enable global interrupts for iic bus
IER = 0x4; //enable Tx FIFO Empty Interrupt [Int(2)]
CR = 0x01; //enable iic controller

/* IIC Master Transmitter with repeated START */
/* 1) Write IIC device @ to Tx_FIFO */
TX_FIFO = write_CH7301;

/* 2) Write data to Tx_FIFO */
TX_FIFO = 0x9C;

/* 3) Write to Control Register to set MSMS=1 and TX=1 */
CR = 0x0D; //TX, MSMS, EN = 1

/* 4) Continue writing data to Tx_FIFO */
TX_FIFO = 0x01;

/* 5) Wait for Transmit FIFO empty interrupt. */
while(!(ISR & 0x04)); //wait until TX_FIFO empty interrupt

/* 6) Write to CR to set RSTA=1 */
CR = 0x2D; //TX, MSMS, EN, RSTA = 1

/* 7) Write IIC device @ to Tx_FIFO */
TX_FIFO = write_CH7301;

/* 8) Write all data except last byte to Tx_FIFO */
TX_FIFO = 0x9F;
TX_FIFO = 0x84;

TX_FIFO = 0xEC;
TX_FIFO = 0xA1;
TX_FIFO = 0x0D;

TX_FIFO = 0xEC;
TX_FIFO = 0xC8;
TX_FIFO = 0x19;

TX_FIFO = 0xEC;
TX_FIFO = 0xC9;
TX_FIFO = 0xC0; //0x00 for bypass mode

TX_FIFO = 0xEC;
TX_FIFO = 0xD6;

/* 9) Wait for Transmit FIFO empty interrupt. */
while(!(ISR & 0x04)); //wait until TX_FIFO empty interrupt

/* 10) Write to CR to set MSMS=0. */
CR = 0x29; //RSTA, TX, EN = 1

/* 11) Write last byte of data to Tx_FIFO */
TX_FIFO = 0x01;
}


From: Arnim on 23 Nov 2009 14:54
Hi,

I've been struggling in the past to generate such color bar test
patterns for both DVI and RGB mode and succeeded after some trial and
error loops. I'm not sure whether this setup can be stripped-down
furthermore, but it worked for me as a first "hello world" before
tackling the more complex topic of displaying an actual image.

The CH7301 required exact waveforms on the H, V & DE pins (I chose VGA
mode 0, 640x480), otherwise the display wouldn't sync. I went for
"sample 2x", i.e. XCLK and XCLK* toggle with 25 MHz, phase shifted by
180 deg. Guess proper XCLK/XCLK* clocking is essential to sample H, V
and DE.

I2C commands were applied according to AN-41, "Figure 4: Single Step
Writes". I.e. n times the sequence, SPC @ ~195 kHz:
1. START condition
2. DAB
3. RAB
4. Data
5. STOP condition
Didn't try auto increment write or similar.

My final settings for this testcase were
0 => (16#9C#, 16#00#), -- Clock Mode Register
1 => (16#9D#, 16#4C#), -- Input Clock Register: sample 2x
-- t_step XCLK behind of data
2 => (16#9F#, 16#80#), -- Input Data Format Register:
-- format #0, H low active, V low active
3 => (16#a1#, 16#00#), -- DAC Control Register:
-- disable HSYNC & VSYNC outputs
4 => (16#b3#, 16#08#), -- TPCP
5 => (16#b4#, 16#16#), -- TPD
6 => (16#b6#, 16#60#), -- TPF
7 => (16#c9#, 16#C0#), -- Power Management Register
-- DVI in normal function, RGB DACs off
8 => (16#c8#, 16#19#), -- TSTP: test pattern


Hope this helps & good luck!
Arnim
From: mmcshmi11 on 23 Nov 2009 18:12
>The CH7301 required exact waveforms on the H, V & DE pins (I chose VGA
>mode 0, 640x480), otherwise the display wouldn't sync. I went for
>"sample 2x", i.e. XCLK and XCLK* toggle with 25 MHz, phase shifted by
>180 deg. Guess proper XCLK/XCLK* clocking is essential to sample H, V
>and DE.

Does "VGA mode 0" refer to the IDF bits? Also, did you just choose 25MHz
randomly because it was less than 36MHz as Table 2: DVI Outputs in the
CH7301 datasheet says?

>I2C commands were applied according to AN-41, "Figure 4: Single Step
>Writes". I.e. n times the sequence, SPC @ ~195 kHz:

Was 195Khz a random choice of speed as well?

>My final settings for this testcase were
> 0 => (16#9C#, 16#00#), -- Clock Mode Register
> 1 => (16#9D#, 16#4C#), -- Input Clock Register: sample 2x
> -- t_step XCLK behind of data
> 2 => (16#9F#, 16#80#), -- Input Data Format Register:
> -- format #0, H low active, V low active
> 3 => (16#a1#, 16#00#), -- DAC Control Register:
> -- disable HSYNC & VSYNC outputs
> 4 => (16#b3#, 16#08#), -- TPCP
> 5 => (16#b4#, 16#16#), -- TPD
> 6 => (16#b6#, 16#60#), -- TPF
> 7 => (16#c9#, 16#C0#), -- Power Management Register
> -- DVI in normal function, RGB DACs off
> 8 => (16#c8#, 16#19#), -- TSTP: test pattern

Did you have to write custom VHDL to do the timings for the V and H pins?
Did you use the 25MHz clock you chose above and the chosen resolution of
640x480 to determine the H and V input lines? Does having the H and V
active low mean that the "active time" for outputting RGB values is when
you drop these signal lines?

I know there are lots of questions here and thanks for your help so far, I
don't know why there isn't better documentation for implementing this
chip...

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From: Arnim on 24 Nov 2009 17:04

>> The CH7301 required exact waveforms on the H, V & DE pins (I chose VGA
>> mode 0, 640x480), otherwise the display wouldn't sync. I went for
>> "sample 2x", i.e. XCLK and XCLK* toggle with 25 MHz, phase shifted by
>> 180 deg. Guess proper XCLK/XCLK* clocking is essential to sample H, V
>> and DE.
>
> Does "VGA mode 0" refer to the IDF bits? Also, did you just choose 25MHz
> randomly because it was less than 36MHz as Table 2: DVI Outputs in the
> CH7301 datasheet says?

With mode 0 I was referring to the standard VGA mode 640x480 @ 60 Hz.
That's not related to any CH7301 settings, though

The 25 MHz is the pixel clock for this mode (25.175 MHz to be precise).
Also see http://tinyvga.com/vga-timing/640x480(a)60Hz

In general, my strategy to get a color bar test pattern was to operate
the CH7301 as if it was used to output image data: Configure and drive
the chip as in the final application, just without video data applied.
I guess the chip won't "do anything for you" except sketching colorful
bars. You need to provide framing, sync timing etc. yourself.

>> I2C commands were applied according to AN-41, "Figure 4: Single Step
>> Writes". I.e. n times the sequence, SPC @ ~195 kHz:
>
> Was 195Khz a random choice of speed as well?

Yes, a frequency within the respective CH7301 spec (it's 25 MHz / 128).

> Did you have to write custom VHDL to do the timings for the V and H pins?

Yes, a set of counters to generate H & V sync signals plus DE. The
CH7301 embeds the horizontal and vertical sync information in the DVI
stream under control of DE. I assume that the color pattern test mode
simply fills in the display information but requires framing from external.

BTW after some experimenting I went for the ODDR2 double data rate
output registers for XCLK/XCLK* and video data and used the
clock-vs-data phase shift feature for the CH7301. Alternatively, one
could trim the video data outputs vs XCLK with DLL resources on the FPGA.

> Did you use the 25MHz clock you chose above and the chosen resolution of
> 640x480 to determine the H and V input lines?

Again, yes. 25 MHz is the pixel clock frequency and it's used to
generate the sync waveforms on H, V & DE. The same way as for VGA
monitors/displays: H sync, V sync - DE is esentially the blanking signal
covering also the front and back porches around active sync.

> Does having the H and V
> active low mean that the "active time" for outputting RGB values is when
> you drop these signal lines?

The VGA mode requires negative polarity on these lines, therefore I set
this configuration and generated active low waveforms on the pins
accordingly.
Video data is accepted by the CH7301 when DE is 1. DE needs to be 0 to
mux the H and V waveforms into the DVI stream.

> I know there are lots of questions here and thanks for your help so far, I
> don't know why there isn't better documentation for implementing this
> chip...

You're welcome :-) I had quite some headaches as well when struggling
with this chip (and the docs). Once it's set up, fine. But until then
the docs don't give you much clue how to start with it.

The DVI spec http://www.ddwg.org/lib/dvi_10.pdf (especially chapter 3)
was helpful. It clarified some of background topics like the meaning of
DE.

Arnim
From: mmcshmi11 on 13 Dec 2009 21:00
Thanks a lot for your help with these settings. We finally got the color
bar output pattern to display via DVI. It came down to not having the right
timings on the DE line, it's amazing how precise everything has to be to
work.

I would like to post more info about using this chip after we get some
video data input, and hopefully output :)

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