Inverting bits
in [DSP]
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From: Jerry Avins on 2 Jan 2010 21:09 Eric Jacobsen wrote: > On 1/2/2010 11:00 AM, Avier wrote: >> suppose if am having a clock frequency of 60 Mhz and i want to invert >> every third bit that is inverting signal at 20Mhz . what could be the >> best solution in terms of least number of storage bits . >> >> i think a counter can be used but how many storage bits we will count >> it? >> >> any other solutions > > The answer depends on what you're trying to optimize. Do you just want > a solution that works? Or a solution with the minimum number of states? > Or a solution with the minimum hardware complexity? Or a solution > with the least power consumption? Or a solution with the least number > of software instructions? > > Three D-flops connected in a ring will do it. I don't know if that will > satisfy your professor, though. Two D flip-flops and a decoder gate for one of the states will do it too. Another decoder for the invert state, and an XOR to do the inversion. Adding the third flip-flop obviates the need for both decoder gates, so it's the better solution. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
From: glen herrmannsfeldt on 2 Jan 2010 21:39 Jerry Avins <jya(a)ieee.org> wrote: (snip, someone wrote) >> Three D-flops connected in a ring will do it. I don't know if that will >> satisfy your professor, though. > Two D flip-flops and a decoder gate for one of the states will do it > too. Another decoder for the invert state, and an XOR to do the > inversion. Adding the third flip-flop obviates the need for both decoder > gates, so it's the better solution. It took me a little while to understand the two flip flops and XOR gates solution, but I believe it is an LFSR. With two FFs as a shift register and one XOR, you can make a three state FSM such that one of the bits will follow the desired pattern. One XOR to invert the data at the appropriate time. With the two other XORs, you should be able to accomodate the appropriate phase with the assumption of a reset signal for the FFs. Many other solutions need an AND, OR, NAND, or NOR gate to decode the appropriate state reset the counter. (I assume a synchronous design.) -- glen
From: dvsarwate on 2 Jan 2010 22:27 On Jan 2, 8:39 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > It took me a little while to understand the two flip flops and > XOR gates solution, but I believe it is an LFSR. With two FFs > as a shift register and one XOR, you can make a three state > FSM such that one of the bits will follow the desired pattern. Yes indeed, the two FF (maximal-length) LFSR with initial loading 11 has output 110110110110....... and so one could use the complement of the output FF bit to feed into > One XOR to invert the data at the appropriate time. to complement every third bit. If you want to complement two out of three bits, feed the output FF bit (not its complement) to the XOR gate. Of course, the LFSR also uses an XOR gate, and there is probably a modulo three counter using fewer transistors than the LFSR design. --Dilip Sarwate
From: robert bristow-johnson on 2 Jan 2010 23:33 On Jan 2, 1:16 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > robert bristow-johnson wrote: > > that being said, it sounds like you need a counter. i'm sure someone > > has a nice compact divide-by-3 counter circuit laying around. it > > would need at least 2 flip-flops in it. > > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > Nope. > > There is about a zillion of ways for making N-state flip-flop, i.e. > flip-flap-flop for 3 states, flip-flap-flup-flop for 4 states, etc. i don't understand what you are referring to by "Nope". was it my first or second or third statement that was inaccurate? just curious. r b-j
From: Vladimir Vassilevsky on 2 Jan 2010 23:39
robert bristow-johnson wrote: > On Jan 2, 1:16 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > >>robert bristow-johnson wrote: >> >>>that being said, it sounds like you need a counter. i'm sure someone >>>has a nice compact divide-by-3 counter circuit laying around. it >>>would need at least 2 flip-flops in it. >> >>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >>Nope. >> >>There is about a zillion of ways for making N-state flip-flop, i.e. >>flip-flap-flop for 3 states, flip-flap-flup-flop for 4 states, etc. > > > i don't understand what you are referring to by "Nope". was it my > first or second or third statement that was inaccurate? You don't have to use two flip-flops to divide by 3. A 3-state counter could be done entirely without flip-flops. VLV |