Inverting bits
in [DSP]
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From: Vladimir Vassilevsky on 3 Jan 2010 01:18 Tim Wescott wrote: > On Sat, 02 Jan 2010 22:39:23 -0600, Vladimir Vassilevsky wrote: > > >>robert bristow-johnson wrote: >> >> >>>On Jan 2, 1:16 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: >>> >>> >>>>robert bristow-johnson wrote: >>>> >>>> >>>>>that being said, it sounds like you need a counter. i'm sure someone >>>>>has a nice compact divide-by-3 counter circuit laying around. it >>>>>would need at least 2 flip-flops in it. >>>> >>>>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Nope. >>>> >>>>There is about a zillion of ways for making N-state flip-flop, i.e. >>>>flip-flap-flop for 3 states, flip-flap-flup-flop for 4 states, etc. >>> >>> >>>i don't understand what you are referring to by "Nope". was it my >>>first or second or third statement that was inaccurate? >> >>You don't have to use two flip-flops to divide by 3. A 3-state counter >>could be done entirely without flip-flops. > > > But there will be some storage someplace, whether you're using a chip > called a 'flip flop' or whether you're doing the same thing with gates. A stupident asked how many BITS are required. My point is there is no necessity of storing 2 bits to represent 3 states. This holds even if the state machine is comprised of binary logic. VLV
From: glen herrmannsfeldt on 3 Jan 2010 01:56 Vladimir Vassilevsky <nospam(a)nowhere.com> wrote: (snip, someone wrote) >>>>>There is about a zillion of ways for making N-state flip-flop, i.e. >>>>>flip-flap-flop for 3 states, flip-flap-flup-flop for 4 states, etc. (someone else wrote) >> But there will be some storage someplace, whether you're using a chip >> called a 'flip flop' or whether you're doing the same thing with gates. > A stupident asked how many BITS are required. My point is there is no > necessity of storing 2 bits to represent 3 states. This holds even if > the state machine is comprised of binary logic. Counting bits isn't always easy. I do agree that you can make a flip-flop-flap with three stable states. I suppose that means that it stores log2(3) bits, since bits should be log2(stable states). But others might say it stores three bits. I suppose I vote for the log2(3), though, if implemented as an extension to the RS FF. If you want one that changes state on a clock, then you need somewhat more, and the resulting device might have more stable states, even if they are not the desired states. For an RST FF, take three 3 input NAND gates, connect the output of each to an input of the other two. Put pull-up resistors on the other inputs. The result has three stable states. Pull one of the resistor connected inputs to ground and it will change to that state. Maybe it should be called a latch instead. Discussion of such a device came up regarding rest rooms in my college dorm. They might have three states: empty, men, women, though some I knew had four states. (empty, men, women, ???) Usually a wheel and pointer were used, but discussion of an electronic indicator device resulted in such FF. In the end, though, everyone was happy with the wheel and pointer. -- glen
From: Jerry Avins on 3 Jan 2010 11:57 Eric Jacobsen wrote: > On 1/2/2010 7:09 PM, Jerry Avins wrote: >> Eric Jacobsen wrote: >>> On 1/2/2010 11:00 AM, Avier wrote: >>>> suppose if am having a clock frequency of 60 Mhz and i want to invert >>>> every third bit that is inverting signal at 20Mhz . what could be the >>>> best solution in terms of least number of storage bits . >>>> >>>> i think a counter can be used but how many storage bits we will count >>>> it? >>>> >>>> any other solutions >>> >>> The answer depends on what you're trying to optimize. Do you just want >>> a solution that works? Or a solution with the minimum number of >>> states? Or a solution with the minimum hardware complexity? Or a >>> solution with the least power consumption? Or a solution with the >>> least number of software instructions? >>> >>> Three D-flops connected in a ring will do it. I don't know if that >>> will satisfy your professor, though. >> >> Two D flip-flops and a decoder gate for one of the states will do it >> too. Another decoder for the invert state, and an XOR to do the >> inversion. Adding the third flip-flop obviates the need for both decoder >> gates, so it's the better solution. >> >> Jerry > > I don't know that I'd call it the "better" solution unless it fits > whatever optimization criterion is specified, and we don't know what > might be (or if the OP said it, I missed it). > > I just tend to try to think of things in simplest terms, and to me a > ring of D-flops that come out of reset with two cleared and one set does > the job, with the peripheral XOR gate doing the inversion. It might not > the better solution for certain optimization problems, but I think it'd > meet many. If flip-flops are a precious resource and gates are > plentiful, then your solution with two flops and a few gates would be > "better". > > These days hardware logic resources are generally so cheap that just > having the discussion about which would be "better" is a > counter-productive waste of time. Just put down the first circuit that > works and move the hell on to the next...! ;) I think of these problems in terms of the number of packages of gates needed to implement them. With ASICs, all bets are off, and fith FPGAs, the criteria can be somewhat different. With four FFs or gates in a package, eliminating a class eliminates a package. That's all. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
From: Jerry Avins on 3 Jan 2010 11:58 Tim Wescott wrote: > On Sat, 02 Jan 2010 21:09:21 -0500, Jerry Avins wrote: > >> Eric Jacobsen wrote: >>> On 1/2/2010 11:00 AM, Avier wrote: >>>> suppose if am having a clock frequency of 60 Mhz and i want to invert >>>> every third bit that is inverting signal at 20Mhz . what could be >>>> the best solution in terms of least number of storage bits . >>>> >>>> i think a counter can be used but how many storage bits we will count >>>> it? >>>> >>>> any other solutions >>> The answer depends on what you're trying to optimize. Do you just >>> want a solution that works? Or a solution with the minimum number of >>> states? >>> Or a solution with the minimum hardware complexity? Or a solution >>> with the least power consumption? Or a solution with the least number >>> of software instructions? >>> >>> Three D-flops connected in a ring will do it. I don't know if that >>> will satisfy your professor, though. >> Two D flip-flops and a decoder gate for one of the states will do it >> too. Another decoder for the invert state, and an XOR to do the >> inversion. Adding the third flip-flop obviates the need for both decoder >> gates, so it's the better solution. >> >> Jerry > > Or, if you're pulling chips off the shelf, a pair of J-K flip flops (in > one chip) will do the job without any decoding at all -- just the one XOR > for the data. Count to three with two FFs and no gate? Jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
From: Muzaffer Kal on 3 Jan 2010 12:17
On Sat, 02 Jan 2010 22:39:23 -0600, Vladimir Vassilevsky <nospam(a)nowhere.com> wrote: > > >robert bristow-johnson wrote: > >> On Jan 2, 1:16 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: >> >>>robert bristow-johnson wrote: >>> >>>>that being said, it sounds like you need a counter. i'm sure someone >>>>has a nice compact divide-by-3 counter circuit laying around. it >>>>would need at least 2 flip-flops in it. >>> >>>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >>>Nope. >>> >>>There is about a zillion of ways for making N-state flip-flop, i.e. >>>flip-flap-flop for 3 states, flip-flap-flup-flop for 4 states, etc. >> >> >> i don't understand what you are referring to by "Nope". was it my >> first or second or third statement that was inaccurate? > >You don't have to use two flip-flops to divide by 3. A 3-state counter >could be done entirely without flip-flops. You need some storage to keep the states in. What you call them is not relevant. An SR latch (or any other state-ful feedback logic) still does a flip and a flop depending on which input you activate. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com |