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From: BrandonD on 11 Jun 2010 11:52
Thanks for the replies.

As for the design, it is a superscalar processor not designed with FPGA in
mind. Currently, I'm just trying to get it running on a Virtex-5 and I
don't care how slow it is. So yes, I am slowing the clock down as well.
Actually, how I was changing the constraints was by changing the frequency
of the clock from the DCM and letting Xilinx detect the constraint for the
clock. The clock into the FPGA and constraints for it have remained the
same. I'll work on speeding it up later.

Without changing the design except the clock period and having nearly all
optimizations on and timing performance design strategy along with normal
extra effort on map and par, I still couldn't meet a cycle time of 40 ns.
Then I only changed the extra effort on map and par from normal to the next
highest - continue on impossible - and it met a 30 ns cycle time. Xilinx
even mentions in the report that "continue on impossible" should not be
needed in normal cases.

I would really like to not have to use "continue on impossible" as it takes
nearly 3 hours just for par. I'm using Xilinx 10.1 so no multi-threading.


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Posted through http://www.FPGARelated.com
From: maxascent on 11 Jun 2010 13:12
You are doing something seriously wrong if it takes 3 hours to p&r. You
need to specify the clock that you want to run the design and then after
synthesis examine the report to see if it has been met. If it hasnt then
you need to investigate the paths that are failing and then modify the
design to make it pass.

Jon

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Posted through http://www.FPGARelated.com
From: BrandonD on 11 Jun 2010 17:34
I've specified the constraint on the clock to the FPGA. That clock goes to
a DCM and Xilinx generates a constraint for the output clock of the DCM.

Synthesis runs fine, I get around a 3 ns cycle time.

I don't get an error about failing timing constraints until after place and
route has completed. I guess I just need to experiment to find out what
works.

>You are doing something seriously wrong if it takes 3 hours to p&r. You
>need to specify the clock that you want to run the design and then after
>synthesis examine the report to see if it has been met. If it hasnt then
>you need to investigate the paths that are failing and then modify the
>design to make it pass.
>
>Jon
>
>---------------------------------------
>Posted through http://www.FPGARelated.com
>

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Posted through http://www.FPGARelated.com
From: jt_eaton on 11 Jun 2010 19:55
>Hi,
>
>I'm working with Xilinx ISE 10.1 and I am having troubles with timing
>constraints.
>
>
>---------------------------------------
>


What is your % of utilization? Is this chip packed to the max?


Have you tried sacrificing a chicken on top of your workstation?


John

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Posted through http://www.FPGARelated.com
From: Symon on 11 Jun 2010 21:45
On 6/11/2010 4:52 PM, BrandonD wrote:
> Thanks for the replies.
>
> As for the design, it is a superscalar processor not designed with FPGA in
> mind.

Hi Brandon,

Wow, you are designing a "superscalar processor" and yet you can't meet
FPGA timing?

Good luck with that!

Syms.
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