Kernel

[PATCH -next] tile: set ARCH_KMALLOC_MINALIGN
The minimum alignment and width of DMA is L2_CACHE_BYTES (because your dma_get_cache_alignment() returns L2_CACHE_BYTES), right? = From: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> Subject: [PATCH -next] tile: set ARCH_KMALLOC_MINALIGN Architectures that handle DMA-non-coherent memory need to set ARCH_KMA... 29 Jun 2010 04:10

sparc: remove homegrown L1_CACHE_ALIGN macro
From: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> Date: Tue, 29 Jun 2010 16:29:01 +0900 Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> Applied, thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in... 29 Jun 2010 04:10

[PATCH -next] tile: remove homegrown L1_CACHE_ALIGN macro
Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> --- arch/tile/include/asm/cache.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index c2b7dcf..ee59714 10... 29 Jun 2010 04:10

proc: unify PROC_DEVICETREE config
On Mon, Jun 28, 2010 at 7:00 PM, Andres Salomon <dilinger(a)queued.net> wrote: Microblaze and PPC both use PROC_DEVICETREE, and OLPC will as well.. put the Kconfig option into fs/ rather than in arch/*/Kconfig. Signed-off-by: Andres Salomon <dilinger(a)queued.net> --- �arch/microblaze/Kconfig | � �8 --... 29 Jun 2010 04:10

[PATCH] alpha: remove homegrown L1_CACHE_ALIGN macro
Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> --- arch/alpha/include/asm/cache.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/alpha/include/asm/cache.h b/arch/alpha/include/asm/cache.h index f199e69..ad368a9... 29 Jun 2010 04:10

[PATCH] sparc: remove homegrown L1_CACHE_ALIGN macro
Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> --- arch/sparc/include/asm/cache.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index 0588b8c..69358b5... 29 Jun 2010 04:10

[PATCH] parisc: remove homegrown L1_CACHE_ALIGN macro
Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp> --- arch/parisc/include/asm/cache.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 45effe6..a05... 29 Jun 2010 04:10

[PATCH] avoid race condition in pick_next_task_fair in kernel/sched_fair.c
Hi, I walked some code in kernel/sched_fair.c in version 2.6.35-rc3, and got the following potential failure: static struct task_struct *pick_next_task_fair(struct rq *rq) { .... if (!cfs_rq->nr_running) return NULL; do { se = pick_next_entity(cfs_rq); set_next_entity(cfs_rq, se); cfs_r... 29 Jun 2010 04:10

Representative
Act as our representative in your region, based on 10% commission to you on whatever transaction made with our customers on behalf of this company. Reply to chi.hangshi(a)gala.net for more details Maria Wong http://www.beiec.com/cn/ -- This message has been scanned for viruses and dangerous content by M... 29 Jun 2010 04:10

[tip:x86/alternatives] x86, alternatives: Use 16-bit numbers for cpufeature index
Commit-ID: 5dc71d49a7c209b77cd257049a2cdb99ed1008c0 Gitweb: http://git.kernel.org/tip/5dc71d49a7c209b77cd257049a2cdb99ed1008c0 Author: tip-bot for H. Peter Anvin <hpa(a)linux.intel.com> AuthorDate: Thu, 10 Jun 2010 00:10:43 +0000 Committer: H. Peter Anvin <hpa(a)zytor.com> CommitDate: Thu, 10 Jun 2010 23:20:... 29 Jun 2010 04:09