Migrating project from Xilinx ISE v7.1 to v11.1
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From: vragukumar on 30 Mar 2010 20:17 Hello, We are trying to migrate a fully functional project from Xilinx ISE v7.1 to Xilinx ISE v11.1. We started off by creating a new project under v11.1 and bringing over all the .v (verilog source) files, .ise file, .xco files and .ucf file. The project synthesizes successfully, however when trying to Implement design, translate fails with several of the following errors (a) NgdBuild 924: input pad net '....' is driving non-buffer primitives (b) NgdBuild 455: logical net '....' has multiple drivers (c) NgdBuild 462: input pad net '....' drives multiple buffers (d) NgdBuild 809: output pad net'....' has an illegal load Has anyone encountered these errors in the past while migrating from an older version of Xilinx ISE to v11.1 ? Why are these caused and how do we get rid off these errors ? Thanks in advance for your help, Regards. Vikram. --------------------------------------- Posted through http://www.FPGARelated.com
From: Ed McGettigan on 31 Mar 2010 11:16
On Mar 30, 5:17 pm, "vragukumar" <vragukumar(a)n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com> wrote: > Hello, > > We are trying to migrate a fully functional project from Xilinx ISE v7.1 to > Xilinx ISE v11.1. We started off by creating a new project under v11.1 and > bringing over all the .v (verilog source) files, .ise file, .xco files and > .ucf file. > > The project synthesizes successfully, however when trying to Implement > design, translate fails with several of the following errors > > (a) NgdBuild 924: input pad net '....' is driving non-buffer primitives > (b) NgdBuild 455: logical net '....' has multiple drivers > (c) NgdBuild 462: input pad net '....' drives multiple buffers > (d) NgdBuild 809: output pad net'....' has an illegal load > > Has anyone encountered these errors in the past while migrating from an > older version of Xilinx ISE to v11.1 ? Why are these caused and how do we > get rid off these errors ? > > Thanks in advance for your help, > Regards. > Vikram. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com These messages indicate that you have a top level port connected to input of an IBUF and other internal logic at the same time and that you have the a top level port connected to an output of an OBUF and other internal logic at the same time. The likely cause is a mixed use of IO buffer instantiation in the Verilog code and IO insertion in synthesis. This can also happen if you are synthesizing modules that have IO insertion turned on or IP cores that are a black-box in the top level synthesis, but have IO buffers included. Ed McGettigan -- Xilinx Inc. |