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From: vragukumar on 9 Apr 2010 18:57
Hello,

We are trying to determine the number of slices that a specific module in
the design consumes upon synthesis. Is there a way to generate a report
that shows resource utilization per module using Xilinx ISE Webpack v11.5
?

Thanks and Regards,
Vikram.

---------------------------------------
Posted through http://www.FPGARelated.com
From: Ed McGettigan on 10 Apr 2010 15:57
On Apr 9, 6:57 pm, "vragukumar"
<vragukumar(a)n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com> wrote:
> Hello,
>
> We are trying to determine the number of slices that a specific module in
> the design consumes upon synthesis. Is there a way to generate a report
> that shows resource utilization per module using Xilinx ISE Webpack v11.5
> ?
>
> Thanks and Regards,
> Vikram.    
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

The synthesis log/report file should contain the amount of LUT,
Registers, RAM and IO were used. The number of slices that this will
ultimately be used is very dependent on the entire design, the
utilization of the device and mapping options.

Ed McGettigan
--
Xilinx Inc.
From: Chris Maryan on 12 Apr 2010 09:01
On Apr 9, 6:57 pm, "vragukumar"
<vragukumar(a)n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com> wrote:
> Hello,
>
> We are trying to determine the number of slices that a specific module in
> the design consumes upon synthesis. Is there a way to generate a report
> that shows resource utilization per module using Xilinx ISE Webpack v11.5
> ?
>
> Thanks and Regards,
> Vikram.    
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

I can't speak for post synthesis resource utilization since I don't
use ISE for synthesis. But for post map, the .mrp file produced by map
has the info you are looking for (look for a big table at the end of
the file).

Chris
From: CP on 13 Apr 2010 02:40
On 10 Apr., 00:57, "vragukumar"
<vragukumar(a)n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com> wrote:
> Hello,
>
> We are trying to determine the number of slices that a specific module in
> the design consumes upon synthesis. Is there a way to generate a report
> that shows resource utilization per module using Xilinx ISE Webpack v11.5
> ?
>
> Thanks and Regards,
> Vikram.    
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

I don't think that ISE gives you that sort of report, Synplify Pro
does, though!
From: Marc Jet on 14 Apr 2010 06:47
This is what you're looking for: http://www.conekt.net/fpgaoptim.html
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