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From: karthikbg on 9 Jan 2007 00:21
Hi,

I need information similar to below for OMAP 5912 and OMAP 5910.
Kindly let me know if there is any pdf / link for the info w.r.t Boot
ROM, Bootloader & Reset Vector.

All 'C5x DSPs carry a 16-bit on-chip maskable programmable ROM (see
Table 1-1 for sizes). The 'C50 and 'C57S DSPs have boot loader
code resident in the on-chip ROM, all other 'C5x DSPs offer the boot
loader code as an option. This memory is used for booting program code
from slower external ROM or EPROM to fast on-chip or external RAM. Once
the custom program has been booted into RAM, the boot ROM space can be
removed from program memory space by setting the MP/MC bit in the
processor mode status register (PMST). The on-chip ROM is selected at
reset by driving the MP/MC pin low. If the on-chip ROM is not selected,
the 'C5x devices start execution from off-chip memory.

The on-chip ROM may be configured with or without boot loader code.
However, the on-chip ROM is intended for your specific program. Once
the program is in its final form, you can submit the ROM code to Texas
Instruments for implementation into your device. For details on how to
submit code to Texas Instruments to program your ROM, see Submitting
ROM Codes to TI.

The interrupt vectors are addressed in program space. These vectors are
soft - meaning that the processor, when taking the trap, loads the
program counter (PC) with the trap address and executes code at the
vector location. Two words are reserved at each vector location for a
branch instruction to the appropriate interrupt service routine (ISR).
Table 8-7 lists the interrupt vector addresses after reset.

At reset, the interrupt vector is mapped absolutely to address 0000h in
program space. However, the interrupt vector can be remapped to the
beginning of any 2K-word page in program space after reset. To do this,
load the interrupt vector pointer (IPTR) bits in the PMST with the
appropriate 2K-word page boundary address. After IPTR is loaded, any
user interrupt vector is mapped to the new 2K-word page.

For example: OPL#05800h,PMST ;Remap vectors to start at 5800h.

In this example, the interrupt vectors move to off-chip program space
beginning at address 5800h. Any subsequent interrupt (except for a
reset) will fetchits interrupt vector from that new location.

For example, if, after loading the IPTR, an INT2 occurs, the interrupt
service routine vector will be fetched from address 5804h in program
space as opposed to address 0004h. This feature lets you move the
desired vectors out of the boot ROM and then remove the ROM from the
memory map.

Once the system code is booted into the system from the boot-loader
code resident in ROM, the application reloads the IPTR with a value
pointing to the new vectors. In the above example, the OPL instruction
is used to modify the IPTR bits in the PMST. This example assumes that
the IPTR bits are currently cleared. To assure that the correct value
for IPTR is set, the bits must be cleared before this instruction is
executed.

Note: The reset vector can not be remapped, because reset loads the
IPTR with 0. Therefore, the reset vector will always be fetched at
location 0000h in program memory. In addition, for the 'C51 and
'C53, 100 words are reserved in the on-chip ROM for device-testing
purposes. Application code written to be implemented in on-chip ROM
must reserve these 100 words at the top of the ROM addresses.

The program memory can reside both on- and off-chip. At reset, the
'C5x device configuration is set by the level on the MP/MC pin. If
this pin is high, the device is configured as a microprocessor, and the
on-chip ROM is not addressed. If this pin is low, the device is
configured as a microcomputer, and the on-chip ROM is enabled

Thanks and Regards,
Karthik Balaguru

From: karthikbg_dsp on 11 Jan 2007 08:23
>Hi,
>
>I need information similar to below for OMAP 5912 and OMAP 5910.
>Kindly let me know if there is any pdf / link for the info w.r.t Boot
>ROM, Bootloader & Reset Vector.
>
>All 'C5x DSPs carry a 16-bit on-chip maskable programmable ROM (see
>Table 1-1 for sizes). The 'C50 and 'C57S DSPs have boot loader
>code resident in the on-chip ROM, all other 'C5x DSPs offer the boot
>loader code as an option. This memory is used for booting program code
>from slower external ROM or EPROM to fast on-chip or external RAM. Once
>the custom program has been booted into RAM, the boot ROM space can be
>removed from program memory space by setting the MP/MC bit in the
>processor mode status register (PMST). The on-chip ROM is selected at
>reset by driving the MP/MC pin low. If the on-chip ROM is not selected,
>the 'C5x devices start execution from off-chip memory.
>
>The on-chip ROM may be configured with or without boot loader code.
>However, the on-chip ROM is intended for your specific program. Once
>the program is in its final form, you can submit the ROM code to Texas
>Instruments for implementation into your device. For details on how to
>submit code to Texas Instruments to program your ROM, see Submitting
>ROM Codes to TI.
>
>The interrupt vectors are addressed in program space. These vectors are
>soft - meaning that the processor, when taking the trap, loads the
>program counter (PC) with the trap address and executes code at the
>vector location. Two words are reserved at each vector location for a
>branch instruction to the appropriate interrupt service routine (ISR).
>Table 8-7 lists the interrupt vector addresses after reset.
>
>At reset, the interrupt vector is mapped absolutely to address 0000h in
>program space. However, the interrupt vector can be remapped to the
>beginning of any 2K-word page in program space after reset. To do this,
>load the interrupt vector pointer (IPTR) bits in the PMST with the
>appropriate 2K-word page boundary address. After IPTR is loaded, any
>user interrupt vector is mapped to the new 2K-word page.
>
>For example: OPL#05800h,PMST ;Remap vectors to start at 5800h.
>
>In this example, the interrupt vectors move to off-chip program space
>beginning at address 5800h. Any subsequent interrupt (except for a
>reset) will fetchits interrupt vector from that new location.
>
>For example, if, after loading the IPTR, an INT2 occurs, the interrupt
>service routine vector will be fetched from address 5804h in program
>space as opposed to address 0004h. This feature lets you move the
>desired vectors out of the boot ROM and then remove the ROM from the
>memory map.
>
>Once the system code is booted into the system from the boot-loader
>code resident in ROM, the application reloads the IPTR with a value
>pointing to the new vectors. In the above example, the OPL instruction
>is used to modify the IPTR bits in the PMST. This example assumes that
>the IPTR bits are currently cleared. To assure that the correct value
>for IPTR is set, the bits must be cleared before this instruction is
>executed.
>
>Note: The reset vector can not be remapped, because reset loads the
>IPTR with 0. Therefore, the reset vector will always be fetched at
>location 0000h in program memory. In addition, for the 'C51 and
>'C53, 100 words are reserved in the on-chip ROM for device-testing
>purposes. Application code written to be implemented in on-chip ROM
>must reserve these 100 words at the top of the ROM addresses.
>
>The program memory can reside both on- and off-chip. At reset, the
>'C5x device configuration is set by the level on the MP/MC pin. If
>this pin is high, the device is configured as a microprocessor, and the
>on-chip ROM is not addressed. If this pin is low, the device is
>configured as a microcomputer, and the on-chip ROM is enabled
>
>Thanks and Regards,
>Karthik Balaguru
>
>

Hi,
I need to know if there is some TI's Bootloader code that takes control
and uses the SRAM as soon as the OMAP 5912 boots up?

Thx in advans,
Karthik Balaguru




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