PN SEQUENCE (zero values)
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From: Jerry Avins on 4 Feb 2010 16:13 Avier wrote: >> On Feb 4, 3:19=A0pm, "Avier" <shahanwark...(a)hotmail.com> wrote: >>> just for check >>> >>> IS there any way to produce a PN sequence from all zero =A0intial > state. >>> that is all zeros in shift regiters >> I believe the all-zeros state is never legal because it would cause >> all subsequent outputs to be zero. >> > > thats the question can we come out of all zeros state Suppose you use an XNOR instead of an XOR? (Don't get too excited. Although all zeros is no longer pathologic, there's another state that is.) Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
From: Al Clark on 4 Feb 2010 17:51 "Avier" <shahanwarkhan(a)hotmail.com> wrote in news:1- KdnQfbRfxWtvbWnZ2dnUVZ_vOdnZ2d(a)giganews.com: > just for check > > > IS there any way to produce a PN sequence from all zero intial state. > > that is all zeros in shift regiters > The all zero state is a the 2n - (2n-1) state. Its next state is itself. You could use an N input NOR connected to each output state. The output of the NOR would be 0 for all situations except the all 0 state. You could take this value and OR with any one of the output states. This would cause an all 0 condition to be changed to one with a single 1 state. At this point the states would change to the 2n-1 sequence. Once in a 2n-1 sequence, the OR function would never cause a change in the next state since you would always be ORing a 0. This is clearly a very bad solution. In software, you just initialize a seed to be non zero. In hardware, the VLV solution adds an inverter to the output of a flip flop. If you then perform a RESET, you have a seed with a single 1, which will avoid the all zero state. Al Clark www.danvillesignal.com
From: glen herrmannsfeldt on 4 Feb 2010 18:05 Al Clark <aclark(a)danvillesignal.com> wrote: (snip) > You could use an N input NOR connected to each output state. The output of > the NOR would be 0 for all situations except the all 0 state. You could take > this value and OR with any one of the output states. This would cause an all > 0 condition to be changed to one with a single 1 state. At this point the > states would change to the 2n-1 sequence. Once in a 2n-1 sequence, the OR > function would never cause a change in the next state since you would always > be ORing a 0. > This is clearly a very bad solution. Why is it so bad? If you compare the cost of being in the wrong state to the cost of the OR gate, is it all that bad? > In software, you just initialize a seed to be non zero. > In hardware, the VLV solution adds an inverter to the output > of a flip flop. If you then perform a RESET, you have a > seed with a single 1, which will avoid the all zero state. And if an alpha particle comes through and it does get into the wrong state then you are stuck. -- glen
From: robert bristow-johnson on 4 Feb 2010 18:25 On Feb 4, 3:19 pm, "Avier" <shahanwark...(a)hotmail.com> wrote: > just for check > > IS there any way to produce a PN sequence from all zero intial state. > > that is all zeros in shift regiters long ago (in the eighties, and it was on a 68K, like my first Mac) i did a sorta MLS in which i inverted the logic whether to XOR the accumulator or not. i think i XORed if the bit shifted out was a 0, not a 1. and i ran experiments to see that it did 2^N - 1 states before getting back to all zeros. that meant that there was some non-zero state that it never did, and i think i found it, but i don't remember if the word representing the skipped state was something i could derive. r b-j
From: Jerry Avins on 4 Feb 2010 18:35
glen herrmannsfeldt wrote: > Al Clark <aclark(a)danvillesignal.com> wrote: > (snip) > >> You could use an N input NOR connected to each output state. The output of >> the NOR would be 0 for all situations except the all 0 state. You could take >> this value and OR with any one of the output states. This would cause an all >> 0 condition to be changed to one with a single 1 state. At this point the >> states would change to the 2n-1 sequence. Once in a 2n-1 sequence, the OR >> function would never cause a change in the next state since you would always >> be ORing a 0. > >> This is clearly a very bad solution. > > Why is it so bad? If you compare the cost of being in the wrong > state to the cost of the OR gate, is it all that bad? It makes the shift register the equivalent of a permanent logic 0. How bad that is depends on the application. >> In software, you just initialize a seed to be non zero. > >> In hardware, the VLV solution adds an inverter to the output >> of a flip flop. If you then perform a RESET, you have a >> seed with a single 1, which will avoid the all zero state. > > And if an alpha particle comes through and it does get into > the wrong state then you are stuck. Jerry -- Engineering is the art of making what you want from things you can get. ����������������������������������������������������������������������� |