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From: sreedevi1988 on 23 Sep 2009 07:20
Hello,

I am trying to implement a fir filter in vhdl.. i want to put the output
sequence into a text file, so that I can use the same text file in MATLAB
and check the frequency response.. The problem I am facing is;;when I try
to simulate thro Modelsim, it gives the following errors...

# ** Warning: fir_low.vhd(57): (vcom-1194) FILE declaration was written
using VHDL 1987 syntax.
# ** Error: fir_low.vhd(89): No feasible entries for subprogram "write".
# ** Error: fir_low.vhd(90): No feasible entries for subprogram
"writeline".
# ** Error: fir_low.vhd(94): VHDL Compiler exiting
# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.

Pls help me out in this regard.

Thank you,
Sreedevi


From: nobody on 23 Sep 2009 11:18
Sreedevi,

Here is a link to a test bench vhdl file: mix_n_uart_test.vhd that was
used to do just what you are attempting.

http://www.mediafire.com/file/y3vnd3jihyy/mix_n_uart_test.vhd

Cy Drollinger
E.R. L.L.C.

From: Dek on 26 Sep 2009 17:04
On 23 Set, 13:20, "sreedevi1988" <sreedevi1...(a)gmail.com> wrote:
> Hello,
>
> I am trying to implement a fir filter in vhdl.. i want to put the output
> sequence into a text file, so that I can use the same text file in MATLAB
> and check the frequency response.. The problem I am facing is;;when I try
> to simulate thro Modelsim, it gives the following errors...
>
> # ** Warning: fir_low.vhd(57): (vcom-1194) FILE declaration was written
> using VHDL 1987 syntax.
> # ** Error: fir_low.vhd(89): No feasible entries for subprogram "write".
> # ** Error: fir_low.vhd(90): No feasible entries for subprogram
> "writeline".
> # ** Error: fir_low.vhd(94): VHDL Compiler exiting
> # ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.
>
> Pls help me out in this regard.
>
> Thank you,
> Sreedevi

If you didn't solve the problem yet, try to post the post the piece of
code

Bye

Dek
From: sreedevi1988 on 29 Sep 2009 00:54
>On 23 Set, 13:20, "sreedevi1988" <sreedevi1...(a)gmail.com> wrote:
>> Hello,
>>
>> I am trying to implement a fir filter in vhdl.. i want to put the
output
>> sequence into a text file, so that I can use the same text file in
MATLAB
>> and check the frequency response.. The problem I am facing is;;when I
try
>> to simulate thro Modelsim, it gives the following errors...
>>
>> # ** Warning: fir_low.vhd(57): (vcom-1194) FILE declaration was written
>> using VHDL 1987 syntax.
>> # ** Error: fir_low.vhd(89): No feasible entries for subprogram
"write".
>> # ** Error: fir_low.vhd(90): No feasible entries for subprogram
>> "writeline".
>> # ** Error: fir_low.vhd(94): VHDL Compiler exiting
>> # ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.
>>
>> Pls help me out in this regard.
>>
>> Thank you,
>> Sreedevi
>
>If you didn't solve the problem yet, try to post the post the piece of
>code
>
>Bye
>
>Dek
>
Hello

---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:27 09/09/2009
-- Design Name:
-- Module Name: fir_plsssssss - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library std;
use IEEE.std_logic_textio.all;
use std.textio.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fir_low is
port(clk: in std_logic
);
end fir_low;

architecture Behavioral of fir_low is
constant n: integer := 24;
type real is range -2147483647.0 TO 2147483647.0;
type b is array(0 to n) of real;
type x is array(0 to n) of real;
--type LINE is access string;
--type TEXT is file of string;
constant m: integer := 486;
type y is array(0 to m) of real;
--signal inpu,c:b :=
(0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0);
signal coeff:b := (0.0013 , 0.0026, 0.0, -0.0072,-0.0072 , 0.0112, 0.0272,
0.0, -0.0581, -0.0538, 0.0875, 0.2971, 0.3988, 0.2971, 0.0875, -0.0538,
-0.0581, 0.0, 0.0272, 0.0112, -0.0072, -0.0072, 0.0, 0.0026, 0.0013);
signal final : y;
signal outinp:y
:=(12.3353,19.8419,26.8143,32.4206,35.9764,37.0465,35.5109,31.5833,25.7799,18.8417,11.6238,4.9678,0.4210,4.0732,5.8150,5.7791,4.3658,2.1608,0.1763,2.0330,2.9548,2.7273,1.4145,0.6521,2.9326,
4.7762,5.5401,4.7104,2.0039,2.5662,8.6736,15.7133,22.8840,29.3042,34.1449,36.7563,36.7692,34.1533,29.2243,22.5971,15.0929,7.6163,1.0201,4.0190,7.0943,8.1182,7.3191,5.1865,2.3760,0.4125,2.5595,3.6353,3.4742,2.2014,0.2088,1.9164,3.4995,3.9021,2.6432,0.5044,5.4577,11.8184,18.9190,25.9152,31.9090,36.0837,37.8286,36.8353,33.1481,27.1624,19.5700,11.2608,3.1955,3.7304,8.8107,11.6218,12.0717,10.3985,7.1190,2.9382,1.3662,5.0657,7.5886,8.5989,8.0340,6.0976,3.2096,0.0751,3.1665,5.5399,6.8204,6.8395,5.6530,3.5220,0.8592,1.8484,4.1256,5.5903,6.0162,5.3657,3.7901,1.5965,0.8099,3.0000,4.5956,5.3339,5.1095,3.9887,2.1930,0.0560,
2.0374,3.7198,4.7049,4.8359,4.1093,2.6726,0.7947,1.1842,2.9129,4.0920,4.5246,4.1490,3.0472,1.4269,0.4163,2.1533,3.4795,4.1680,4.1082,3.3229,1.9627,0.2767,1.4324,2.8625,3.7652,3.9890,3.5042,2.4064,0.8980,0.7491,2.2419,3.3190,3.7953,
3.5944,2.7601,1.4475,0.1057,1.6223,2.8348,3.5322,3.5971,3.0248,1.9234,0.4930,1.0102,2.3197,3.2059,3.5163,3.2016,2.3231,1.0414,0.4132,1.7821,2.8238,3.3570,3.2916,2.6441,1.5336,0.1602,1.2311,2.3941,3.1248,3.2971,2.8844,1.9637,0.7016,0.6765,1.9260,2.8266,3.2210,3.0427,2.3265,1.2024,0.1284,1.4291,2.4698,3.0675,3.1188,2.6174,1.6547,0.4034,0.9137,2.0629,2.8417,3.1137,2.8328,2.0510,0.9088,0.3901,1.6153,2.5498,3.0292,2.9702,2.3848,1.3785,0.1308,1.1365,2.1990,2.8688,3.0283,2.6505,1.8036,0.6387,0.6371,1.7974,2.6369,3.0072,2.8436,2.1758,1.1230,0.1276,1.3541,2.3391,2.9081,2.9607,2.4879,1.5740,0.3812,0.8787,1.9822,2.7338,3.0000,2.7338,1.9822,0.8787,0.3812,1.5740,2.4879,2.9607,2.9081,2.3391,1.3541,0.1276,1.1230,2.1758,2.8436,3.0072,2.6369,1.7974,0.6371,0.6387,1.8036,2.6505,3.0283,2.8688,2.1990,1.1365,0.1308,
1.3785,2.3848,2.9702,3.0292,2.5498,1.6153,0.3901,0.9088,2.0510,2.8328,3.1137,2.8417,2.0629,0.9137,0.4034,1.6547,2.6174,3.1188,3.0675,2.4698,1.4291,0.1284,1.2024,2.3265,3.0427,3.2210,2.8266,1.9260,0.6765,0.7016,1.9637,2.8844,3.2971,3.1248,2.3941,1.2311,0.1602,1.5336,2.6441,3.2916,3.3570,2.8238,1.7821,0.4132,1.0414,2.3231,3.2016,3.5163,3.2059,2.3197,1.0102,0.4930,1.9234,3.0248,3.5971,3.5322,2.8348,1.6223,0.1057,1.4475,2.7601,3.5944,3.7953,3.3190,2.2419,0.7491,0.8980,2.4064,3.5042,3.9890,3.7652,2.8625,1.4324,0.2767,1.9627,3.3229,4.1082,4.1680,3.4795,2.1533,0.4163,1.4269,3.0472,4.1490,4.5246,4.0920,2.9129,1.1842,0.7947,2.6726,4.1093,4.8359,4.7049,3.7198,2.0374,0.0560,2.1930,3.9887,5.1095,5.3339,4.5956,3.0000,0.8099,1.5965,3.7901,5.3657,6.0162,5.5903,4.1256,1.8484,0.8592,3.5220,5.6530,6.8395,6.8204,5.5399,3.1665,0.0751,3.2096,6.0976,8.0340,8.5989,7.5886,5.0657,1.3662,2.9382,7.1190,10.3985,12.0717,11.6218,8.8107,3.7304,3.1955,11.2608,19.5700,27.1624,33.1481,36.8353,37.8286,36.0837,31.9090,25.9152,18.9190,11.8184,5.4577,0.5044,2.6432,3.9021,3.4995,1.9164,0.2088,2.2014,3.4742,3.6353,2.5595,0.4125,2.3760,5.1865,7.3191,8.1182,7.0943,4.0190,1.0201,7.6163,15.0929,22.5971,29.2243,34.1533,36.7692,36.7563,34.1449,29.3042,22.8840,15.7133,8.6736,2.5662,2.0039,4.7104,5.5401,4.7762,2.9326,0.6521,1.4145,2.7273,2.9548,2.0330,0.1763,2.1608,4.3658,5.7791,5.8150,4.0732,0.4210,4.9678,11.6238,18.8417,25.7799,31.5833,35.5109,37.0465,35.9764,32.4206,26.8143,19.8419,12.3353,5.1523,0.9452,5.3937,7.8981,8.4559,7.3370,5.0222,2.1117,0.7780,3.1146,4.5285,4.8600,4.1667,2.6940,0.8137,1.0549,2.5280,3.3288,
3.3348,2.5940,1.3066,0.2208,1.6416,2.6409);
signal i,j : integer := 0;
begin
process (clk,i)
file outfile:text is out "G:\work1.txt";
variable inp:x:=
(3.0000,2.6409,1.6416,0.2208,1.3066,2.5940,3.3348,3.3288,2.5280,1.0549,0.8137,2.6940,4.1667,4.8600,4.5285,3.1146,0.7780,2.1117,5.0222,7.3370,8.4559,7.8981,5.3937,0.9452,5.1523);
variable temp: real := 0.0;
variable temp1: real := inp(0);
variable y:real := 0.0;
VARIABLE out_l : line;
variable inpu,c:b :=
(0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0);
variable outinp_slv_var : std_logic_vector(15 downto 0);
variable outinp_int : integer := 0;
variable int :integer := 0;
begin
if(rising_edge(clk)) then
y := 0.0;
for i in 0 to n loop
inpu(i) := inp(i);
end loop;
for i in 0 to (n-1) loop
temp := inp(i+1);
inp(i+1) := temp1;
temp1 := temp;
end loop;
if (j <m) then
inp(0) := outinp(j);
j <= j+1;
end if;
for s in 0 to n loop
c(s) := (coeff(s)*inpu(s));
end loop;
for t in 0 to n loop
y := (y + c(t));
end loop;
final(i) <= y;
if (i<m) then
i <= i+1;
end if;
outinp_int := integer(y* 10000.0);
outinp_slv_var := conv_std_logic_vector(outinp_int,16);
--WRITE(out_l,y);
write (out_l, outinp_slv_var);
write( outfile , out_l);
end if;
end process;
end Behavioral;

Hello

This is the code I wrote.. Pls neglect so many numbers (input and
co-efficient values)The doubts I ve is:
a) Do i ve to declare what a line and text is? I mean
type LINE is access string;
type TEXT is file of string;

b) Here, I've tried to convert a real number into a std logic vector n
write into a text...Can't I directly put in a number like 2.3456 into a
text file? Anyway, neither of them is working..

Pls help me!!!



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