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From: Jon on 21 Jun 2010 19:09
Hi guys,
at first some background information:
I'm doing a study project for some weeks now which is about "VHDL
development environment for FPGA".

The first goal was to set up ISE WebPack under Ubuntu Linux to work with
the Nexys 2 board. This took me a lot of time because of the bad
documentation of Digilent concerning the programming of the board under
Linux. With the script nexys2prog I found a way to do this.

Second task was to implement the MIPS I compatible CPU Plasma. I was able
to do this with mainly some pinout-changes (ucf file).

Third task was to build a gcc-cross-toolchain for mips-elf.

Now I'm able to run programs (located in internal RAM on FPGA,
ram_image.vhd) on the CPU and to communicate with the board via
UART<->RS-232<->terminal.
I want to load programs to external RAM via bootldr and execute them.

Now my questions:
1. What is the cause that I did not find any information on the internet
about an implementation of Plasma on Nexys 2 ???

2. How can I interface the RAM Chip on Nexys 2 ?
The Problem: Plasma needs 32 bit access, but the memory bus of the board is
only 16 bits wide.

This module
(http://opencores.org/websvn,filedetails?repname=plasma&path=%2Fplasma%2Ftrunk%2Fvhdl%2Fplasma_if.vhd)
interfaces with the Spartan-3 Starter Kit Board
(http://www.digilentinc.com/Data/Products/S3BOARD/S3BOARD_RM.pdf - page
11).
The memory interface of Nexys2 looks like this (RAM = IC13)
(http://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdf - page
13-14)

My idea: Memory should be a black box from CPU perspective which provides
32 bit access. In this black box, maybe with double clock: first 16 bit of
data is at address x, second 16 bit is at address y. These two chunks of
data should be read sequentially and then merged to a 32 bit word, write
access vice versa.

IMHO this will just be a few lines of code..but I just have no clue how to
do it in VHDL.

Anyone...ideas, suggestions ?

Greetings, Jon



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