SOLVED: Problems with simulation of amforth in VMLAB...
in [FPGA]
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From: wzab on 14 Sep 2009 14:30 A few months ago I've reported problems related to simulation of amforth ( http://amforth.sf.net ) in the VMLAB ( http://www.amctools.com/vmlab.htm) details are described here: http://www.amctools.com/cgi-bin/yabb2/YaBB.pl?num=1240766206 I have discovered that the problems are caused by the fact, that VMLAB does not simulate correctly behaviour of the AVR when the flash memory is reprogrammed but only with '1' changed to '0'. The amforth uses "inteligent" algorithm, which erases the page only when any '0' is changed to '1' otherwise the page is reprogrammed without erasing, which causes, that VMLAB assumes that operation fails. If anyone wants to simulate the amforth with the current version of the VMLAB, it is necessary to switch off this mechanism (only for the version used in simulation, do not do it in the version burned into the real AVR): The change has to done in file core/words/istore_nrww.asm I have done it in the way which keeps the size and location of the code unchanged (only the jump destination is modified). The original amforth 3.5 code: [code] ; an erase cycle is only necessary ; when changing a bit from 0 to 1 .dw XT_OVER .dw XT_OVER .dw XT_IFETCH .dw XT_INVERT .dw XT_AND .dw XT_DOCONDBRANCH .dw PFA_ISTORE_WRITE .dw XT_DUP .dw XT_SPMERASE PFA_ISTORE_WRITE: .dw XT_DUP .dw XT_SPMWRITE .dw XT_SPMRWW .dw XT_DROP .dw XT_DROP .dw XT_R_FROM .dw XT_INTRESTORE .dw XT_EXIT [/code] The changed amforth code - simulates correctly (erase always): [code] ; an erase cycle is only necessary ; when changing a bit from 0 to 1 .dw XT_OVER .dw XT_OVER .dw XT_IFETCH .dw XT_INVERT .dw XT_AND .dw XT_DOCONDBRANCH ; Jump to the next instruction - erase always .dw PFA_ISTORE_ERASE PFA_ISTORE_ERASE: .dw XT_DUP .dw XT_SPMERASE PFA_ISTORE_WRITE: .dw XT_DUP .dw XT_SPMWRITE .dw XT_SPMRWW .dw XT_DROP .dw XT_DROP .dw XT_R_FROM .dw XT_INTRESTORE .dw XT_EXIT [/code] -- HTH & Regards, Wojtek |