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From: Terje Mathisen "terje.mathisen at on 14 Mar 2010 05:46
Stephen Fuld wrote:
> On 3/11/2010 10:15 AM, Terje Mathisen wrote:
>> The 8086 model did have a 16-bit bus as well as an 8-byte instruction
>> buffer, which meant that at least during those instructions that didn't
>> load or store anything, the bus could be used to load one or two
>> upcoming opcodes.
>
> Yes, and IIRC, the 8088 has a slightly larger instruction buffer as a
> counter to the smaller bus width. Again, an intelligent response to what
> was available and needed.
>
The opposite:

The 8088, as I showed above, had almost zero opportunity to ever load
anything into that prefetch buffer, so they _reduced_ the size from 8 to
6 bytes.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
From: Terje Mathisen "terje.mathisen at on 14 Mar 2010 05:48
Tim McCaffrey wrote:
> In article<hnhiqf$gap$1(a)news.eternal-september.org>,
> SFuld(a)alumni.cmu.edu.invalid says...
>> Yes, and IIRC, the 8088 has a slightly larger instruction buffer as a
>> counter to the smaller bus width. Again, an intelligent response to
>> what was available and needed.
>>
>
> Actually, I think the 8088's was 4 bytes, and the 8086 was 6.

Oops, I think you're right! (I wrote 6 vs 8 in my previous post. :-()

The key here is that Intel knew that the 8088 had far less opportunity
to ever load anything into the prefetch buffer, so they could safely
reduce the size of it.

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
From: Stephen Fuld on 14 Mar 2010 14:07
On 3/14/2010 1:46 AM, Terje Mathisen wrote:
> Stephen Fuld wrote:
>> On 3/11/2010 10:15 AM, Terje Mathisen wrote:
>>> The 8086 model did have a 16-bit bus as well as an 8-byte instruction
>>> buffer, which meant that at least during those instructions that didn't
>>> load or store anything, the bus could be used to load one or two
>>> upcoming opcodes.
>>
>> Yes, and IIRC, the 8088 has a slightly larger instruction buffer as a
>> counter to the smaller bus width. Again, an intelligent response to what
>> was available and needed.
>>
> The opposite:
>
> The 8088, as I showed above, had almost zero opportunity to ever load
> anything into that prefetch buffer, so they _reduced_ the size from 8 to
> 6 bytes.

Thanks to Tim and Terje for correcting my recollections. But despite my
error, I still maintain the original point, that these decisions were
made using good engineering judgment and not out of ignorance of caches,
or certainly of different bus widths.



--
- Stephen Fuld
(e-mail address disguised to prevent spam)
From: Terje Mathisen "terje.mathisen at on 14 Mar 2010 15:59
Stephen Fuld wrote:
> On 3/14/2010 1:46 AM, Terje Mathisen wrote:
>> Stephen Fuld wrote:
>>> On 3/11/2010 10:15 AM, Terje Mathisen wrote:
>>>> The 8086 model did have a 16-bit bus as well as an 8-byte instruction
>>>> buffer, which meant that at least during those instructions that didn't
>>>> load or store anything, the bus could be used to load one or two
>>>> upcoming opcodes.
>>>
>>> Yes, and IIRC, the 8088 has a slightly larger instruction buffer as a
>>> counter to the smaller bus width. Again, an intelligent response to what
>>> was available and needed.
>>>
>> The opposite:
>>
>> The 8088, as I showed above, had almost zero opportunity to ever load
>> anything into that prefetch buffer, so they _reduced_ the size from 8 to
>> 6 bytes.
>
> Thanks to Tim and Terje for correcting my recollections. But despite my
> error, I still maintain the original point, that these decisions were
> made using good engineering judgment and not out of ignorance of caches,
> or certainly of different bus widths.
>
>
>


--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
From: Terje Mathisen "terje.mathisen at on 14 Mar 2010 15:59
Stephen Fuld wrote:
> On 3/14/2010 1:46 AM, Terje Mathisen wrote:
>> The 8088, as I showed above, had almost zero opportunity to ever load
>> anything into that prefetch buffer, so they _reduced_ the size from 8 to
>> 6 bytes.
>
> Thanks to Tim and Terje for correcting my recollections. But despite my
> error, I still maintain the original point, that these decisions were
> made using good engineering judgment and not out of ignorance of caches,
> or certainly of different bus widths.

Sure, we're in full/violent agreement about _that_!
:-)

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
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