From: Terje Mathisen on
glen herrmannsfeldt wrote:
> Many processors, I believe starting with the 8080 have a half carry
> flag in their 8 bit adders. The DAA instruction, decimal adjust for
> addition, adds the appropriate 6 depending on that bit and the regular
> carry bit.

Sure. The problem is that these operations explicitely work on just one
or possibly two digits, stored within a single byte.

Speedwise, this cannot compete with a SIMD setup which stores 8 BCD
digits in a 32-bit register, even though the SIMD code requires more steps.

Terje
--
- <Terje.Mathisen(a)hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"
From: glen herrmannsfeldt on
Terje Mathisen wrote:

> glen herrmannsfeldt wrote:

>>Many processors, I believe starting with the 8080 have a half carry
>>flag in their 8 bit adders. The DAA instruction, decimal adjust for
>>addition, adds the appropriate 6 depending on that bit and the regular
>>carry bit.

> Sure. The problem is that these operations explicitely work on just one
> or possibly two digits, stored within a single byte.

Well, for an eight bit processor that is all one would expect. As far
as I know, intel kept this same bit on the 8086 for compatibility. The
8086 was supposed to be source backwards compatible with the 8080.

> Speedwise, this cannot compete with a SIMD setup which stores 8 BCD
> digits in a 32-bit register, even though the SIMD code requires more steps.

Set flags for overflow from each nybble and it should work for a 64 bit
register. I think even with a carry lookahead adder you can still get
those bits out.

-- glen

From: Eric Smith on
torbenm(a)diku.dk (Torben ýgidius Mogensen) writes:
> The 6502 had a BCD "mode" (set and cleared with SED and CLD
> instructions) that made additions and subtractions use BCD. IIRC, the
> arithmetic operatons didn't take extra cycles when in decimal mode.

No extra cycle on the NMOS parts. Most if not all of the CMOS parts
did add an extra cycle for BCD add and subtract.