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From: aleksa on 5 Dec 2009 18:28
> I'd strongly suggest reading and following the guidelines I outlined
Kevin Jennings, THANK YOU for all your input!
I have finally found the error and it was a coding error.
It wasn't READY after all, although READY was involved.
There are some regs in the FPGA that both master and
slave CPUs can access. Master has access when READY='1'.
Input to those regs are ADDRESS and DATA so I have this MUXes:
REGADDR <= MASTER_ADDR when READY='1' else SLAVE_ADDR;
REGDATA <= MASTER_DATA when READY='1' else SLAVE_DATA;
Sometimes, there was a write to those regs at the exact
point in time when READY changes which resulted in
selecting random regs and random data.