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From: BruceMcF on 19 Feb 2010 16:30
Finally, note that for the C128, if the datasette port is not in use,
a line-only interface could put a0-a2 on the three datasette I/O
lines, after setting #$01 to all output, /CS0 on PA2, and /Rd and /Wr
on SP1 and SP2.

When initializing, set up SP1 and SP2 with the minimum length clock
cycle - 2 clocks per phase or 4 clocks per bit, and be sure to store #
$FF in both the SP1 and SP2 register so that the process always starts
with /Rd and /Wr high.

When making sure it works, after PA2 has been pulled low, store #$81
to get a nice long low cycle.

Generating /Rd /Wr off of an active-low demux connected to PC2 will be
a faster interface, but this one ought to be just wiring things up and
then programming.

If interrupts are disabled during the process of generating the /Rd
or /Wr flag, this version can be sped up by shifting the store to SP1
or SP2 earlier in the process and storing a byte that holds the line
high while the rest of the process is taking place. Since the process
of setting up I/O, and storing a byte then pulling down PA2 or pulling
down PA2 then waiting to read a byte will be less than 32 clocks, it
should be possible to store a value in the SP1 or SP register at the
outset.

Alternatively, if its desired to optimize block reads (for loading
runnable code modules, etc.), then hook SP1 to /CSO and SP2 to /Rd,
with PA2 connected to /Wr. Tie CLK1 and CLK2 together, set the SP1 and
SP2 both as output, CLK1 as output and CLK2 as input.

So for read:
* Set PortB to input, SP2 to output
** START
* block interupt
* Write $#FD to SP2
* Write $#F8 to SP1, cycle starts
* 12 clocks later, read PortB
* have 20 clocks to release interrupt, read and store with block read,
release interupt until looping back to ** START

For write:
* Set PortB to output.
** START
* block interupt
* Write $#FF to SP2
* Write $#xx to SP1, cycle starts
* Write data byte to PortB
* "xx" should be bringing SP1 low now
* Pull PA2 low
* Pull PA2 high
* "xx: should be bringing SP1 high now
* clear interupt, write and index if block write

Seems like around 40 to 42 clocks per byte plus overhead for block
reads and writes. For a 256 byte block,
...
LDA PORTB ; 3
STA (TARGET),Y ; 4/5
INY ; 2
BEQ PBRD_DONE ; 3/2
NOP
NOP
NOP
BNE IDE_RD1 ; 3
PBRD_DONE:

.... so its somewhere around 25%-50% slower than an interface built
around an active low demux and the PC2 handshake line on reading or
writing PortB.
From: BruceMcF on 21 Feb 2010 00:13
On Feb 1, 4:13 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote:
> I've recently built a "$5" IDE harddrive interface for a
> Synertek SYM-1 (see <http://www.twitpic.com/photos/Sym_Biosys>),
> and now the idea is to bung one onto my C128.
> For that, I'll need 16 bits of I/O...

Isn't the cartridge port the fastest 8-bit IDE port?

Use one of the two /IO select lines, depending on whether you want it
high or low as /CS0.

/IOx => /CS0
a0-a2 => a0-a2

Wire-or (with diodes, I'd guess):

/IOx + /CLK + a3 = /Read
/IOx + /CLK + a4 = /Write

So use the first eight address for reads, the next eight addresses for
write.

Hmmm ... I think I may have changed my mind on whether to bid for one
of those port expanders.
From: BruceMcF on 23 Feb 2010 00:03
On Feb 1, 4:13 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote:
> I've recently built a "$5" IDE harddrive interface for a
> Synertek SYM-1 (see <http://www.twitpic.com/photos/Sym_Biosys>),
> and now the idea is to bung one onto my C128.
> For that, I'll need 16 bits of I/O...

> I'm thinking this idea of using a 74LS373 would be the way to go:
>     <http://www.compeng.dit.ie/staff/tscarff/Parallel_Port/SPP_interface.JPG>
> (Where this PC Printer Port expander uses STROBE, I'd be using
> the User Port's PA2, probably into a 74LS139.)

After going all the way around the block reading datasheets, the 74373
is indeed the simplest solution. The key is to make use of the PC2 and
the fact that the 74373 data outputs go high impedence when the latch
output goes high.

(1) Hook the eight data lines to the eight PortB data lines ... the
latch will be locked when PA2 is pulled low.

(2) IDE a0-a2, /Wr, /Rd come from the latch (two spare lines) ... /CS1
is tied high.

(2) PA2 to Pin 11, LE (Latch enable) and also to IDE /CS0

(3) PC2 to Pin 1, 3 state output enable

Writing:

With PA2 high, set PortB to all output and then write the desired a0-
a2, /Rd=1, /Wr=0 setting to PortB. Latch output enable will then drop
for 1 clock, but /CS0 is high so there will not be any read or write.

Then pull PA2 low, and write the data to Port B. Now with /CS0, when
either /Rd or /Wr are low for one clock, the data on PortB will be
written. The data is stable since the PC2 transition is one clock
after the port is written.

You can leave /CS0 low and continue writing for a block write ... PC2
going high will result in all the latched values going high, then the
next write, /Wr will be be low again for a second write cycle, and so
on.

The main inner loop for the block loop is:

LDY #0
IDEWR1:
LDA PORTB
STA (BUF),Y
INY
BNE IDEW1
INC BUF+1
IDEWR2
LDA PORTB
STA (BUF),Y
INY
BNE IDEW2
....

Reading:

With PA2 high, set PortB to all output and then write the desired a0-
a2, /Rd=1, /Wr=0 setting to PortB. Latch output enable will then drop
for 1 clock, but /CS0 is high so there will not be any read or write.

Then pull PA2 low, set PortB to input. Read Port B (this first read is
dummy data). Then PC2 will drop, and the new input will be written
into PortB. Pull PA2 high and read PortB again for the actual data.

I'm not sure, but I think block read mode should work as block write
mode, with the first read a dummy and the last read of the segment
done with PA2 high.

Anyway, I have some User port interfaces on the way to start playing
around later this Spring.
From: Chris Baird on 1 Mar 2010 01:28
> Isn't the cartridge port the fastest 8-bit IDE port?

Not if you include the lead-in time to design, test, and build a full-on
memory-mapped interface, and having to wait for weeks to get the
finger-board edge connectors to suit. Practical Reasons. Whereas the
'wires-only' user port idea was built in an afternoon with parts I
already had at hand.

It's moot now, as another 'afternoon' project was using a 2-wire
handshake parallel connection between the User Port and the
(bidirectional) parallel printer port of a Linux system. A lot simpler
(and less of a chore to build) than the previous straight-through wire
IDE adaptor, and it still gets a respectible 8.5kB/s. I've got it all in
EPROM now, and it's now onto the next stage of the Vintage Computer
Development Project..

--
Chris
From: BruceMcF on 1 Mar 2010 23:29
On Mar 1, 1:28 am, Chris Baird <ab...(a)brushtail.apana.org.au> wrote:
>  > Isn't the cartridge port the fastest 8-bit IDE port?

> Not if you include the lead-in time to design, test, and build a full-on
> memory-mapped interface, and having to wait for weeks to get the
> finger-board edge connectors to suit.

I was thinking more stripped ends of the required wires from a ribbon
cable from an IDE ribbon connector, taped to a board thick enough so
that the wires make contact. I can cycle down to the Shack to get
that ...

(get it, cycle down to the Shack, they sponsor Lance Armstrong ...
oh, never mind)

.... while I had to wait three or four days to get a User port
connector.

But I'm still waiting to get my AV plug ... the old C64 TV connector
does not fit my antenna plug on my 7" LCD TV, so I still don't know if
the damn thing works. I'm worried about getting it, I bought a IEC
daisychain cable from the same guy and got a box of 5.25" floppies
instead.

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