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From: whygee on 29 Mar 2010 06:39
Sandro wrote:
> A little bit OT...
Yes, this thread would better suit the comp.arch group.
There are great CPU architecture specialists there :-)

> Regards
> Sandro
yg

--
http://ygdes.com / http://yasep.org
From: "Andy "Krazy" Glew" on 30 Mar 2010 23:12
The two hardware datastructures supporting out of order execution:

Reservation stations.

And, less beautifully, the register renaming map.

But then I am biased.

--

Really, I do think that the reservation stations are beautiful. Even the naive CAM implementation. Especially since
there are more efficient implementations that are logically equivalent.

I am also pretty high on bit matrix schedulers.

From: "Andy "Krazy" Glew" on 30 Mar 2010 23:13
On 3/29/2010 7:39 PM, MitchAlsup wrote:
> The most memorable hardware structure is the vector indirect
> addressing mode.
>
> Mitch


Aagh! No! Although work I did on that veered towards reservation stations, which I like.

Nvidia has shown that vector indirect is unnecessary on a SIMT.

Although^2, it turns out that very similar hardware is needed for SIMT scalar indirect.
From: "Andy "Krazy" Glew" on 1 Apr 2010 11:35
On 3/30/2010 9:15 PM, glen herrmannsfeldt wrote:
> In comp.arch.fpga "Andy \"Krazy\" Glew"<ag-news(a)patten-glew.net> wrote:
>> The two hardware datastructures supporting out of order execution:
>
>> Reservation stations.
>
>> And, less beautifully, the register renaming map.
>
> Both from the IBM 360/91, as far as I know.
>
> S/360 has only four floating point registers, so register
> renaming was pretty important for out-of-order execution.
>
> OK, how about imprecise interrupts?
>
> -- glen


I never really knew how the 360/91 did register renaming. I don't think it used a RAM style map. I think it used CAMs.

I actually asked Tomasulo this, but he never really answered the question.
From: "Andy "Krazy" Glew" on 1 Apr 2010 11:46
> In article<houi8s$rdm$1(a)naig.caltech.edu>,
>> OK, how about imprecise interrupts?

Not a good idea.
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