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From: honio on 21 May 2010 09:22
Hello,

i have a strange problem with my FIFO created with Xilinx CoreGenerator for
a Spartan 3a.

I have a FIFO with a read and write clock separately.
The simulation of the design, including the FIFO signals are at
this address:

http://eech.org/fifoProblem.jpg

After a wr_en and a Din and a wr_clk the empty signal stays at '1'!
I need a correct empty signal to be able to read from the FIFO.

I would be very glad, if someone could help me to solve this problem.



---------------------------------------
Posted through http://www.FPGARelated.com
From: John McCaskill on 21 May 2010 10:00
On May 21, 8:22 am, "honio" <claudio(a)n_o_s_p_a_m.eech.org> wrote:
> Hello,
>
> i have a strange problem with my FIFO created with Xilinx CoreGenerator for
> a Spartan 3a.
>
> I have a FIFO with a read and write clock separately.
> The simulation of the design, including the FIFO signals are at
> this address:
>
> http://eech.org/fifoProblem.jpg
>
> After a wr_en and a Din and a wr_clk the empty signal stays at '1'!
> I need a correct empty signal to be able to read from the FIFO.
>
> I would be very glad, if someone could help me to solve this problem.
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com


The empty signal is a read side signal and is synchronous to the read
clock. Your simulation does not show any activity on read clock in
that time frame, so I would not expect any change on empty. Take a
look at a longer time frame that has a few read clocks to see what is
happening.

Regards,

John McCaskill
www.FasterTechnology.com
From: Jan Pech on 21 May 2010 10:16
On Fri, 2010-05-21 at 08:22 -0500, honio wrote:
> Hello,
>
> i have a strange problem with my FIFO created with Xilinx CoreGenerator for
> a Spartan 3a.
>
> I have a FIFO with a read and write clock separately.
> The simulation of the design, including the FIFO signals are at
> this address:
>
> http://eech.org/fifoProblem.jpg
>
> After a wr_en and a Din and a wr_clk the empty signal stays at '1'!
> I need a correct empty signal to be able to read from the FIFO.
>
> I would be very glad, if someone could help me to solve this problem.
>
>
>
> ---------------------------------------
> Posted through http://www.FPGARelated.com


Do you expect to get any empty status output without a read clock?

Jan

From: honio on 21 May 2010 10:57
>Do you expect to get any empty status output without a read clock?
>
>Jan
>

Yes i wanted to have the empty flag assigned when i first write to the
fifo.

The readclock is much slower than the writeclock! But i use the empty
signal on with the writeclock rate.

Think i have to change fifo to a common clock.



---------------------------------------
Posted through http://www.FPGARelated.com
From: Peter Alfke on 21 May 2010 13:53
On May 21, 7:57 am, "honio" <claudio(a)n_o_s_p_a_m.n_o_s_p_a_m.eech.org>
wrote:
> >Do you expect to get any empty status output without a read clock?
>
> >Jan
>
> Yes i wanted to have the empty flag assigned when i first write to the
> fifo.
>
> The readclock is much slower than the writeclock! But i use the empty
> signal on with the writeclock rate.
>
> Think i have to change fifo to a common clock.
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

You need a read clock edge to change the Empty flag. You might use a
faster read clock and control the read operation with read enable.

Here is a deeper explanation:
Empty is really only important for the read operation. The write side
"does not care whether the FIFO is empty".
The Empty rising edge is naturally caused by a read, but the falling
(trailing) edge is obviously caused by a write, and would thus
naturally be synchronous with the write clock. When read and write
clocks are different and uncorrelated, this would insert an
asynchronous falling edge into the read control logic, leading to
unreliable operation and metastable problems. To prevent this, the
falling edge of Empty is internally re-synchronized to the read clock.
And therefore you need a read clock to initiate any change of the
externally visible Empty flag.

Asynchronous dual-clock FIFO design is tricky, that's why you were
well-advised to use a "canned" solution that is proven to be reliable
under all conditions.
Just use a multiple of the intended read clock frequency, and control
the read operation with an enable.

Peter Alfke, formerly with Xilinx Applications, now retired.
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