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From: chrisdekoh on 19 Apr 2010 12:49
Hi,

does anyone know if there is such a thing as clock IO for Xilinx
FPGA?? If i were to design my own PCB board with an FPGA on it, do i
necessarily have to route the clock from the on-board oscillator
directly only to the clock IO pins?

din consider this before, but thought i get some opinions to be sure

thanks
Chris
From: Ed McGettigan on 19 Apr 2010 13:03
On Apr 19, 9:49 am, chrisdekoh <chrisde...(a)gmail.com> wrote:
> Hi,
>
> does anyone know if there is such a thing as clock IO for Xilinx
> FPGA?? If i were to design my own PCB board with an FPGA on it, do i
> necessarily have to route the clock from the on-board oscillator
> directly only to the clock IO pins?
>
> din consider this before, but thought i get some opinions to be sure
>
> thanks
> Chris

Yes, certain pins are defined as clock pins. You need to read the
"Package and Pinout User Guide" for the specific family that you are
using for more information.

Ed McGettigan
--
Xilinx Inc.
From: Gabor on 19 Apr 2010 16:17
On Apr 19, 1:03 pm, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote:
> On Apr 19, 9:49 am, chrisdekoh <chrisde...(a)gmail.com> wrote:
>
> > Hi,
>
> > does anyone know if there is such a thing as clock IO for Xilinx
> > FPGA?? If i were to design my own PCB board with an FPGA on it, do i
> > necessarily have to route the clock from the on-board oscillator
> > directly only to the clock IO pins?
>
> > din consider this before, but thought i get some opinions to be sure
>
> > thanks
> > Chris
>
> Yes, certain pins are defined as clock pins.  You need to read the
> "Package and Pinout User Guide" for the specific family that you are
> using for more information.
>
> Ed McGettigan
> --
> Xilinx Inc.

You really need to read the clocking section of the main user
guide for your FPGA family. This describes the types of clock
pins and any routing considerations. Many newer FPGA families
have regional as well as global clock resources. Also many have
pins that are labeled as global clock, but can only be used
as the negative half of a differential clock pair. Furthermore
some FPGA's have limitations routing clocks from the same edge
due to limited buffer resources. This is one case where it
really helps to try to build a design before locking down the
pinout of your board.

Regards,
Gabor

PS - Any pin of a Xilinx FPGA can be a clock source if you are
willing to use non-dedicated routing from the pin to the clock
buffer. This sort of connection should be used only as a last
resort as the non-dedicated route has a large delay component
that depends on voltage temperature and process. That being
said, if your clock is just an oscillator that goes nowhere
else in the system (i.e. you have no signals that are phase
related to the clock coming into your FPGA) you can use any pin.
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