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From: Markus Meng on 1 Oct 2006 11:46
Hi,

can you tell a little what kind of software versions besides MIG
you are using. Concerning the FIFO16 issues, this has been covered
within MIG V1.6 in the generated source code. Are you using VHDL
or Verilog?

Anyhow search for the Answer Record 22462 in the source code. You
will discover the fix being made in the src.

I have a board working for a customer with 6 DDR2 memories being
connected to a LX60 from Xilinx. It seems to work ;-)

However I use the older concept with the IDELAY logic to delay incoming
data from the DDR2 memory. As you have the option I don't see what
you have choosen so far.

Concerning your simulation problem, have you applied reset for the
DCM being involved?

In order to support you more, we need more info of how you did
use the MIG generated code in your design.

What MIG generates is something you may use as a starter.
However in my very personal opinion and experience with it, there is no
way out, but you need to walk through all the code and try to understand
what Xilinx does in its DDR2 controller design.
Then you may change things and make things easier ...

You can email me directly. Maybe I'am able to assist you.

Best Regards
Markus



waishanl(a)gmail.com schrieb:
> Joseph Samson wrote:
>> waishanl(a)gmail.com wrote:
>>> Hi! i am having problem to communicate between virtex4 fx60 to 512
>>> SODIMM. I use the MIG1.6 to generate a controller. I add one module
>>> into the design, change some names and run ModelSim. The simulation
>>> looks fine. So, i use the ICE tools to get my bit file. When i check
>>> all the report, I saw the map report have the follwoing message:
>>>
>>> WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please
>>> note that
>>> there are additional requirements for the FIFO16 to guarantee full
>>> functionality. For more information regarding requirements for the
>>> FIFO16
>>> primitive, please see Answer Record 22462.
>>>
>>> is that going to cause me fail on the design? I didn't fine any .edn or
>>> ngc file in the folder that MIG generate.
>>>
>>> I also run the time simulation, it didn't match with the funcational
>>> simulation. Seems like signal start fail in 200ns. Am i missing
>>> anything?
>>>
>>> In addition, I chipscope the signal. It seems like data did get in the
>>> fifo. But the controller never request a read. Any ideas?
>> There has been quite a bit written lately about DDR2 and MIG in this
>> newsgroup. Search for ddr2 and MIG. I recommend replacing the FIFO16s
>> with FIFOs generated by CoreGen that don't use the FIFO16 primitive. I
>> had problems with the address/command FIFO. It would be empty, but still
>> indicate that it had data, so the same memory cycle would run forever.
>>
>> ---
>> Joe Samson
>> Pixel Velocity
>
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