verilog multiplexer
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From: maxascent on 1 Jan 2010 04:51 I would like to create a generic multiplexer in Verilog were I can set the number of inputs and data bits. I can create something using 2 input multiplexers cascaded but this produces a priority structure which uses more logic resources. If anyone can give me a clue as to if it is possible that would be great. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: glen herrmannsfeldt on 1 Jan 2010 06:36 maxascent <maxascent(a)yahoo.co.uk> wrote: > I would like to create a generic multiplexer in Verilog were I can set the > number of inputs and data bits. I can create something using 2 input > multiplexers cascaded but this produces a priority structure which uses > more logic resources. If anyone can give me a clue as to if it is possible > that would be great. The synthesis tools that I know of will easily optimize out any difference that you might be thinging about, at least for FPGA targets. (You did post to comp.arch.fpga.) That is especially true for LUT4 architecture FPGAs. I believe the usual generated form is more like an N to 2**N decoder, followed by AND/OR logic. That is especially true if it is more than one bit wide, which requires only one decoder. -- glen
From: maxascent on 1 Jan 2010 07:16 I did a quick experiment using Synplify were I created 2 multiplexers of 4 inputs with 64-bit data, one using my cascaded 2 input mux and another using a case statement. The one with the case statement used less resorces. So either I have coded the first incorrectly or Synplify is interpreting the code differently. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Benjamin Krill on 1 Jan 2010 08:05 On Fri, 2010-01-01 at 06:16 -0600, maxascent wrote: > I did a quick experiment using Synplify were I created 2 multiplexers of 4 > inputs with 64-bit data, one using my cascaded 2 input mux and another > using a case statement. The one with the case statement used less resorces. > So either I have coded the first incorrectly or Synplify is interpreting > the code differently. I did the experience that is depends on the FPGA type (Lut type, ...) and vendor (maybe tools). So, I think it is a good practice to test it for the different factors. cheers ben
From: John_H on 1 Jan 2010 17:57
On Jan 1, 4:51 am, "maxascent" <maxasc...(a)yahoo.co.uk> wrote: > I would like to create a generic multiplexer in Verilog were I can set the > number of inputs and data bits. I can create something using 2 input > multiplexers cascaded but this produces a priority structure which uses > more logic resources. If anyone can give me a clue as to if it is possible > that would be great. > > Jon > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com One of the simplest and most consistent multiplexers I've used is with arrays of registers or wires. wire [p:0] my_sel; wire [n:0] my_array [m:0]; // assign m+1 my_array values to the desired inputs reg [n:0] my_output; // always @(posedge clk) my_output <= my_array[my_sel]; |