From: Luca Barbieri on
> We already do that kind of stuff, using
> kernel_fpu_begin()..kernel_fpu_end(). �We went through some pain a bit
> ago to clean up "private hacks" that complicated things substantially.

But that saves the whole FPU state on the first usage, and also
triggers a fault when userspace attempts to use it again.
Additionally it does a clts/stts every time which is slow for small
algorithms (lke the atomic64 routines).

The first issue can be solved by using SSE and saving only the used
registers, and the second with lazy TS flag restoring.

How about something like:

static inline unsigned long kernel_sse_begin(void)
{
struct thread_info *me = current_thread_info();
preempt_disable();
if (unlikely(!(me->status & TS_USEDFPU))) {
unsigned long cr0 = read_cr0();
if (unlikely(cr0 & X86_CR0_TS)) {
clts();
return cr0;
}
}
return 0;
}

static inline void kernel_sse_end(unsigned long cr0)
{
if (unlikely(cr0))
write_cr0(cr0);
preempt_enable();
}

to be improved with lazy TS restoring instead of the read_cr0/write_cr0?
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From: Luca Barbieri on
> This really sounds like the wrong optimization. �These functions aren't
> exactly all that complex in assembly (which would also allow them to be
> simple cli/do stuff/sti), and instead relying on gcc features which may
> or may not be well supported on x86 is inviting breakage down the line.
>
> That is particularly damaging, since the remaining 486-class users tend
> to be deeply embedded and thus we only find problems later.

There is the downside of adding a whole 386/486-specific implementation.

It's not too hard though, and if we don't care about 486 SMP, it may
be a better option.
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From: H. Peter Anvin on
On 02/18/2010 10:49 AM, Luca Barbieri wrote:
>> This really sounds like the wrong optimization. These functions aren't
>> exactly all that complex in assembly (which would also allow them to be
>> simple cli/do stuff/sti), and instead relying on gcc features which may
>> or may not be well supported on x86 is inviting breakage down the line.
>>
>> That is particularly damaging, since the remaining 486-class users tend
>> to be deeply embedded and thus we only find problems later.
>
> There is the downside of adding a whole 386/486-specific implementation.
>
> It's not too hard though, and if we don't care about 486 SMP, it may
> be a better option.

We don't care about 486 SMP. And yes, I think it is a better option.
At least an assembly option, once implemented, will *stay* implemented
and won't break due to some obscure gcc change.

-hpa

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From: H. Peter Anvin on
On 02/18/2010 10:42 AM, Luca Barbieri wrote:
>> We already do that kind of stuff, using
>> kernel_fpu_begin()..kernel_fpu_end(). We went through some pain a bit
>> ago to clean up "private hacks" that complicated things substantially.
>
> But that saves the whole FPU state on the first usage, and also
> triggers a fault when userspace attempts to use it again.
> Additionally it does a clts/stts every time which is slow for small
> algorithms (lke the atomic64 routines).
>
> The first issue can be solved by using SSE and saving only the used
> registers, and the second with lazy TS flag restoring.
>

Again, I want to see a strong use case before even *considering* making
the rules we already have any more complex.

-hpa
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From: Yuhong Bao on


> We don't care about 486 SMP.�
Yep, I remember when a previous patch broke 486 SMP support and since then, seemed like nobody cared.The closest to such a system I have seen was P5 systems using the 82489DX APIC.Anybody have a dmesg of such a system?
Yuhong Bao
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