From: Kolja Sulimma on 16 Oct 2005 06:04
David Geirsson wrote:
> Hi all,
> I am new to logic design in general, but I am getting an FPGA
> development board (the Spartan-3 board from xilinx) and I hope to make
> a small circuit for connecting to an old microcomputer and some SRAM.
> For this project, I will need a bunch of (~60) 5V I/O lines, but the
> FPGA's lines are all 3.3V logic. How do people generally go about
> handling this sort of thing? It seems ridiculous to put 8-bit data
> buffers on the lines, as there would be a ridiculous amount of them. Is
> there a good level converter circuit with loads of I/O lines or some
Others allready mentioned that series resistor are a way to do it if you
do not need the highest speeds.
Let me add that you can stay fully TTL compliant by this approach
because 5V TTL only requires you to drive the outputs to 2.4V with a drive
strength of 2mA. You can add 1k or more to each pin and still meet that
From: John Adair on 16 Oct 2005 07:12
Ignoring the possible issues with slow edge you can increase the value to
reduce the current. Just slows down how fast the interface can run. Using
the simplist 2.2RC (did I remenber right) as you transition time you can
balance your values against speed.
To avoid lifting supplies you can add a ballast load(resistor) or use a
push-pull regulator like we use on sodimm reference voltages(LP2996).
Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 PCI Development
"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message
> On Sat, 15 Oct 2005 22:27:16 -0500, "GPE"
> <See_my_website_for_email(a)cox.net> wrote:
>>"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in
>>> On Sun, 16 Oct 2005 00:10:52 +0100, "John Adair"
>>> <loseitintheblackhole(a)blackholesextreme.co.uk> wrote:
>>>>There are a few ways to do this. Bus switches are the common way
>>>>when you don't want a significant timing penalty. We us these on our
>>>>development products and you can see 20 bit devices on out Broaddown2
>>>>Mini-Can products. However these are not for the quick knock-up circuit
>>>>they are on a 0.4 mm lead pitch. As a bit a plug when using our boards
>>>>stand-alone the PCI interface on our boards can be used as 50 bit, 5V
>>>>tolerant, interface using an optional connection module. There are other
>>>>high bit count devices available as bus switches, or even 5V tolerant
>>>>but the same problems with non-simple packages will generally occur.
>>>>We have a module planned that may help with bus switches on-board but
>>>>probably 10-12 weeks before that is likely to be available. This module
>>>>be in DIL format and can be incorporated into stripboards circuits etc
>>>>use with anyone's boards.
>>>>Otherwise you can use resistors to limit the current into the Spartan-3
>>>>using the internal protection diodes to limit voltage. If the I/O
>>>>set at 3.3V, or higher, then you need to be careful as the limit on the
>>>>Spartan-3 I/O is 4.05V. 3.3V + 0.7(diode) = 4V. Usually with this
>>>>you drop the I/O voltage slightly to 3.0-3.2V as we do on most of our
>>>>products to improve the safety margin. If your board hasn't got Vccio
>>>>enough then you can use either schottky diodes, or appropriate zeners to
>>>>to cut in before the internal protection diodes do.
>>> We interfaced a 5-volt uP to a Spartan3 with just series resistors. It
>>> worked fine, but the high levels on the logic lines snuck through the
>>> S3 esd diodes and pulled the 3.3 volt supply up to about 3.7. We
>>> scaled down the programming resistors on the 3.3 volt regulator
>>> radically to dump enough supply current and hold the 3.3 down where it
>>Curious, Xilinx recommends 300 ohm resistors. Which ones were you using?
> 180's I think, because we have lots of them in teeny quad packages,
> and also because there's lots of capacitance on the uP side of the
> bus... multilayer traces all over the place. I guess the Vccio current
> of the Spartan was pretty low, too. Actually, it worked fine at 3.7
> volts, but it failed our test procedure in the part where we verify
> all the power rail voltages.