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From: airol on 7 Jan 2010 06:12
Hello there,

I'm adding custom IP (DCT core) to EDK 9.1. Input (xin) is write to
slv_reg0 while output (dct2d_out) is write to slv_reg1.

I'm following a tutorial from
http://www.ee.cooper.edu/~stefan/projects/tutorials/edk_custom_ip/edk_custom_ip.pdf

I can write and read from the slv_reg0 (for input, xin), but I cannot
read the value from slv_reg1 (for dct2d_out). The output enable,
rdy_out is used to enable writing dct2d_out value to the slv_reg1.

Can anyone point me out any correction should i make.

Thanks in advance.

=============================================
user_logic.vhd

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------

entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to
C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to
C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to
C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to
C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to
C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic
component dct

PORT (

CLK : IN std_logic;

RST : IN std_logic;

xin : IN std_logic_vector(7 downto 0); --
8 bit input.

dct_2d : OUT std_logic_vector(11 downto 0);

rdy_out : OUT std_logic);

END component;

------------------------------------------
-- Signals for user logic slave model s/w accessible register
example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 1);
signal slv_reg_read_select : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;

signal dct_2d_i : std_logic_vector(0 to 11);
signal rdy_out_i : std_logic;

begin

--USER logic implementation added here
dct_0 : dct

port map (

CLK => Bus2IP_Clk,

RST => Bus2IP_Reset,

xin => slv_reg0(0 to 7),

dct_2d => dct_2d_i,

rdy_out => rdy_out_i

);


slv_reg_write_select <= Bus2IP_WrCE(0 to 1);
slv_reg_read_select <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0);-- or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);

-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
else
case slv_reg_write_select is
when "10" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data
(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "01" =>
-- for byte_index in 0 to (C_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

write_enable_process : process (Bus2IP_Clk) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then

if Bus2IP_Reset = '1' then
slv_reg1 <= (others => '0');
else
case rdy_out_i is
when '0' => slv_reg1 <= (others => '0');
when '1' => slv_reg1 <= dct_2d_i;
when others => slv_reg1 <= (others => '0');
end case;
end if;
end if;

end process write_enable_process;

-- slv_reg1(13 to 15) <= (others => '0');

-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1 ) is
begin

case slv_reg_read_select is
when "10" => slv_ip2bus_data <= slv_reg0;
when "01" => slv_ip2bus_data <= slv_reg1;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;
IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';

end IMP;

========================================================

========================================================

my software application code.

#include "xparameters.h"
#include "stdio.h"
#include "my_dct.h"
#include "xbasic_types.h"

Xuint32 *baseaddr_p = (Xuint32 *)XPAR_MY_DCT_0_BASEADDR;

int main()
{


Xuint32 baseaddr, i;



// Check that the peripheral exists



XASSERT_NONVOID(baseaddr_p != XNULL);

baseaddr = (Xuint32) baseaddr_p;

Xuint16 data[8], data_read;

data[0]=0x28;

data[1]=0x21;

data[2]=0x21;

data[3]=0x16;

data[4]=0x1A;

data[5]=0x28;

data[6]=0x24;

data[7]=0x1A;

for(i=0; i<8; i++)
{
MY_DCT_mWriteSlaveReg0(baseaddr, data[i]);
data_read = MY_DCT_mReadSlaveReg0(baseaddr);
xil_printf("data write to reg0: 0x%04X\r\n", data_read);
}


for(i=0; i<8; i++)
{
data_read = MY_DCT_mReadSlaveReg1(baseaddr);
xil_printf("data read from reg1: 0x%04X\r\n", data_read);
}

return 0;

}

=============================================================================

============================================================================

this is the ouput from terminal.

data write to reg0: 0x0028
data write to reg0: 0x0021
data write to reg0: 0x0021
data write to reg0: 0x0016
data write to reg0: 0x001A
data write to reg0: 0x0028
data write to reg0: 0x0024
data write to reg0: 0x001A
data read from reg1: 0x0000
data read from reg1: 0x0000
data read from reg1: 0x0000
data read from reg1: 0x0000
data read from reg1: 0x0000
data read from reg1: 0x0000
data read from reg1: 0x0000
data read from reg1: 0x0000

======================================================================
 | 
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Prev: PMC or XMC based on Altera parts (preferably Stratix)
Next: Difference among Virtex Families, FPGA Books