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From: newzhnd on 13 Jun 2010 19:52
Help !!! The megawizard in Quartus 2 does not seem to support generating
small roms & rams using the LUT
tables, only using the M9K memory blocks. Any way to generate small roms &
rams using the logic cells ?
I'm looking for something similar to Xilinx distributed memory generator.
TIA.

Jim


From: glen herrmannsfeldt on 13 Jun 2010 20:04
newzhnd <nobody(a)home.com> wrote:

> Help !!! The megawizard in Quartus 2 does not seem to support generating
> small roms & rams using the LUT
> tables, only using the M9K memory blocks. Any way to generate small roms &
> rams using the logic cells ?
> I'm looking for something similar to Xilinx distributed memory generator.
> TIA.

Can't you just generate them in ordinary verilog or VHDL?

For Xilinx, the RAM arrays are synchronous, so it has to generate
LUT RAM (or ROM) if it is used asynchronously.

-- glen
From: newzhnd on 13 Jun 2010 20:16
I'd rather not write verilog & specify each rom or ram word individually.
Cyclone 2 supports logic cell usage
for rom or ram. I'm surprised cyclone 3 doesn't. Xilinx allows either LUT
or block memory for ram or rom.
Nothing to do with sync or async.

"glen herrmannsfeldt" <gah(a)ugcs.caltech.edu> wrote in message
news:hv3rmb$ul3$1(a)speranza.aioe.org...
> newzhnd <nobody(a)home.com> wrote:
>
>> Help !!! The megawizard in Quartus 2 does not seem to support
>> generating
>> small roms & rams using the LUT
>> tables, only using the M9K memory blocks. Any way to generate small roms
>> &
>> rams using the logic cells ?
>> I'm looking for something similar to Xilinx distributed memory generator.
>> TIA.
>
> Can't you just generate them in ordinary verilog or VHDL?
>
> For Xilinx, the RAM arrays are synchronous, so it has to generate
> LUT RAM (or ROM) if it is used asynchronously.
>
> -- glen


From: Nial Stewart on 14 Jun 2010 08:06
"newzhnd" <nobody(a)home.com> wrote in message news:XaeRn.26714$%u7.16071(a)newsfe14.iad...
> Help !!! The megawizard in Quartus 2 does not seem to support generating small roms & rams using
> the LUT
> tables, only using the M9K memory blocks. Any way to generate small roms & rams using the logic
> cells ?
> I'm looking for something similar to Xilinx distributed memory generator.


Altera devices can't implement LUT based distributed memory, this is one of
Xilinx's heavily patented uniqe selling points!

You just have to use device logic or M9Ks.


Nial.


From: Gabor on 14 Jun 2010 08:25
On Jun 14, 8:06 am, "Nial Stewart"
<nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> "newzhnd" <nob...(a)home.com> wrote in messagenews:XaeRn.26714$%u7.16071(a)newsfe14.iad...
> > Help !!!   The megawizard in Quartus 2 does not seem to support generating small roms & rams using
> > the LUT
> > tables, only using the M9K memory blocks.  Any way to generate small roms & rams using the logic
> > cells ?
> > I'm looking for something similar to Xilinx distributed memory generator.
>
> Altera devices can't implement LUT based distributed memory, this is one of
> Xilinx's heavily patented uniqe selling points!
>
> You just have to use device logic or M9Ks.
>
> Nial.

If it's so heavily patented, why do Lattice devices support
distributed RAM? There must be some work-arounds to the
existing patents.
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