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From: Robert Myers on 3 Dec 2009 17:09 On Dec 3, 4:03 pm, "Del Cecchi" <delcecchioftheno...(a)gmail.com> wrote: > > In CMOS, the transistors don't really have a switching time. Rather > there is delay associated with charging or discharging the gate > (transistor gate, not logic gate) between the on voltage and the off > voltage (usually VDD and Gnd respectively). Since both gate > capacitance and current capability of a transistor are proportional to > width, this leads to the concept of gate limited delay, or the minimum > delay of a gate with no interconnect driving an identical gate, and > driven by an identical gate. > > To the gate delay one must add the effects of the interconnect and fan > out. > > So far as I know, most of the layers in a 45 nm process are 45 nm > although typically the last few metal layers are thicker and coarser > for lower resistance power distribution. > > Unless things have changed recently I don't think anybody is doing 15 > levels of interconnect. Which is it that limits clock speed, though? Irreducible gate delay, or interconnect delay? Since I understand (after a less-than-polite exchange here) that interconnect delay *also* depends on gate delay (because of the use of repeaters on long interconnects), I am prepared for the answer that there is no simple answer, but I would be delighted if someone gave it a shot. Robert.
From: Del Cecchi on 3 Dec 2009 22:06 "Robert Myers" <rbmyersusa(a)gmail.com> wrote in message news:1d2e8d2a-a35c-4d8a-a578-d2bf1d1efd4a(a)s20g2000yqd.googlegroups.com... On Dec 3, 4:03 pm, "Del Cecchi" <delcecchioftheno...(a)gmail.com> wrote: > > In CMOS, the transistors don't really have a switching time. Rather > there is delay associated with charging or discharging the gate > (transistor gate, not logic gate) between the on voltage and the off > voltage (usually VDD and Gnd respectively). Since both gate > capacitance and current capability of a transistor are proportional > to > width, this leads to the concept of gate limited delay, or the > minimum > delay of a gate with no interconnect driving an identical gate, and > driven by an identical gate. > > To the gate delay one must add the effects of the interconnect and > fan > out. > > So far as I know, most of the layers in a 45 nm process are 45 nm > although typically the last few metal layers are thicker and coarser > for lower resistance power distribution. > > Unless things have changed recently I don't think anybody is doing > 15 > levels of interconnect. Which is it that limits clock speed, though? Irreducible gate delay, or interconnect delay? Since I understand (after a less-than-polite exchange here) that interconnect delay *also* depends on gate delay (because of the use of repeaters on long interconnects), I am prepared for the answer that there is no simple answer, but I would be delighted if someone gave it a shot. Robert. ----------------- In CMOS there really isn't an irreducible gate delay as such. But the minimum transition times are limited by the inherent capacitance and the current drive of the transistors. So if you build an inverter that uses transistors of a size that carry 1 ma with a gate voltage of 1.5volts (vdd)and the capacitance of the output node is 50 fF then even if you apply an instantaneous voltage to the input it will take the output 37.5 pS to get to the threshold of VDD/2. Any wiring or fan out will increase that time. Since wires are resistive, the delay of a wire increases faster than the length of the wire. (distributed RC circuit), so cutting the wire in pieces and inserting buffers is a win, in general. If the buffers had zero delay you could use many and reduce the delay of a long wire to an arbitrary extent. But they don't so you can't. You can play around with the numbers by using the first approximation to the FET equations. Id=constant*w/l*(Vgs-Vt)Vds (linear region) Id=1/2*constant*w/l(Vgs-Vt)**2 note that the input and output capacitances are approximately proportional to width of devices and length is determined by process. (yes, I ignored fringing. too bad) del
From: "Andy "Krazy" Glew" on 4 Dec 2009 00:47
Robert Myers wrote: > On Dec 3, 4:03 pm, "Del Cecchi" <delcecchioftheno...(a)gmail.com> wrote: > >> In CMOS, the transistors don't really have a switching time. Rather >> there is delay associated with charging or discharging the gate >> (transistor gate, not logic gate) between the on voltage and the off >> voltage (usually VDD and Gnd respectively). Since both gate >> capacitance and current capability of a transistor are proportional to >> width, this leads to the concept of gate limited delay, or the minimum >> delay of a gate with no interconnect driving an identical gate, and >> driven by an identical gate. >> >> To the gate delay one must add the effects of the interconnect and fan >> out. >> >> So far as I know, most of the layers in a 45 nm process are 45 nm >> although typically the last few metal layers are thicker and coarser >> for lower resistance power distribution. >> >> Unless things have changed recently I don't think anybody is doing 15 >> levels of interconnect. > > Which is it that limits clock speed, though? Irreducible gate delay, > or interconnect delay? Since I understand (after a less-than-polite > exchange here) that interconnect delay *also* depends on gate delay > (because of the use of repeaters on long interconnects), I am prepared > for the answer that there is no simple answer, but I would be > delighted if someone gave it a shot. Both. The total delay through any critical loop. A critical loop like the path from the output of an ALU, through wires and bypass muxes back to its input, and through the ALU to that same output bit. Or, equivalently, to the next bit, in a carry save form. Or, longer, for carry propagate. Or like the path the input to the AGU (Address Generation Unit), through the AGU, to the cache decoders, through the cache data array, and back through alignment and bypass to the input of the AGU. You'll hear different answers from different people. E.g. one guy might say interconnect is 50% of your favorite critical loop, while another guy says that it is only 10%. When you look closely, you will see that the first guy considered all of the wires between transistors as interconnect, while the second guy only considers wires between cells, e.g. gates, to be interconnect, but thinks that wires within gates are not interconnect. With the former definition, 50% was not unreasonable. You don't go too far wrong thinking of interconnect as 100%, or, rather, Tcrit = max(interconnect delay, charging time) and totally ignore switching time. That is, in fact, the simplistic timing model that I use to do an initial evaluation of al of my designs. Or, at least, that I used, back in the P4/Wmt/Fireball era. After that, learn about logical effort. After that, model it. |