From: Antti on
jacko schrieb:

> Frank Buss wrote:
> > jacko wrote:
> >
> > >
> > > link to quartus II files
> >
> > This looks like a net list or something like this. I have only ISE WebPack
> > installed and I don't know how to display it. Do you have a picture of it?
> i think ahdl custom to altera. there tool is web downloaded. could
> notget the xilinx tool to download after 5 attempts.
> website more specific.
> the zip file is current project design files in quartus II version 6,
> but still have to design instruction sequencing unit. thought of using
> an 8 cycle simple instruction execution, for a very compact IP core.
> also decided that modular forth in instancable blocks would be most
> flexible.
> it is going to evolve as a 16n design, as all carry can happen along
> multiple instances to make any 16*n word size, but i have to decide how
> the program word width may or may not expand to the word size.
> i hope to get wishbone and avalon bus interfaces too, but this is not
> my immediate priority.
> i intend a serial bus standard to allow connected multicore designs,
> each core having 128KB memory.
> does anyone know how to export a quartus project as VHDL?
> cheesr
> jacko


you possible have to handconvert the AHDL to VHDL :(
thats the reason I suggested using non-vendor HDL in the first place.