Compiling a design in Quartus that doesn't fit
in [FPGA]
|
From: General Schvantzkoph on 11 Mar 2010 10:05 I want to be able to generate an encrypted netlist of a core using Quartus. Does Quartus have a switch that allows you to compile a design that doesn't fit into an FPGA? The issue is that the ports on the core exceed the number of pins on any device.
From: Nial Stewart on 11 Mar 2010 10:25 "General Schvantzkoph" <schvantzkoph(a)yahoo.com> wrote in message news:7vsf4tFaprU4(a)mid.individual.net... >I want to be able to generate an encrypted netlist of a core using > Quartus. Does Quartus have a switch that allows you to compile a design > that doesn't fit into an FPGA? The issue is that the ports on the core > exceed the number of pins on any device. There are settings to allow you to compile lower level entites for incremental compilation, although I can't remember what they are. A quick search shows that 'virtual pin' might be what you're looking for, or lead in the right direction. Nial.
From: General Schvantzkoph on 11 Mar 2010 11:23 On Thu, 11 Mar 2010 15:25:58 +0000, Nial Stewart wrote: > "General Schvantzkoph" <schvantzkoph(a)yahoo.com> wrote in message > news:7vsf4tFaprU4(a)mid.individual.net... >>I want to be able to generate an encrypted netlist of a core using >> Quartus. Does Quartus have a switch that allows you to compile a design >> that doesn't fit into an FPGA? The issue is that the ports on the core >> exceed the number of pins on any device. > > > There are settings to allow you to compile lower level entites for > incremental compilation, although I can't remember what they are. > > A quick search shows that 'virtual pin' might be what you're looking > for, or lead in the right direction. > > > Nial. Thanks, that sounds like what I want.
|
Pages: 1 Prev: Xilinx ISE Webpack Schematics Next: fastest multiplier for dsps |