From: pini_45 on
>Is anyone aware of a design controlling the 'I2C_controller_core' from
> I read very good review of this core, but it needs to
>controlled by either a state machine or a small processor. The current
>only works at the 'byte' level.
>I'd like to be able to tell it: write those 37 bytes to that slave
>address...or read 48 bytes from that slave address...
>I thought I'd ask before starting to write the state machine!
>This message was sent using the comp.arch.fpga web interface on
this night be interesting to you
This design uses the open core's I2C master. The core's CPU interface is
modified from WISHBONE to AMBA/APB. The latter is done in order to test the
core and its new APB interface with LEON processor. LEON is written in VHDL
therefor the core's VHDL RTL design is tested. The core also contains a
test bench and simulation model for I2C slave, written in VERILOG. From the
VERILOG test bench only the initialization procedure is taken and the I2C
slave model is translated to VHDL.

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