E1 clock problem with Spartan3e...
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From: Morppheu on 28 Jan 2010 11:59 On Jan 13, 1:35 pm, rickman <gnu...(a)gmail.com> wrote: > I'm not sure where this thread started, I don't see a message before > Nico's post Jan 11. Did you post your code? > > Your design is using about 10% of the LUTs as routing, which does tend > to happen when your LUT usage rises using up much of the routing > resources. The main offender that I can see is the use of almost 50% > of the LUTs as DP RAM. I am guessing that these are being used for > FIFO buffers. Can you reduce the number of LUTs used for buffering or > are they all required? > > As to the clocking issue, I don't know what the problem is exactly. > Why can't you use the E1 clock? What pin is the E1 clock connected to > on the S3 part? I would hope it is connected to a DCM or at least a > clock input. > > It is hard to suggest much more without more insight into what your > design is doing. > > Rick > > On Jan 12, 9:00 am, Morppheu <jdemam...(a)gmail.com> wrote:> > Why use the internal clock? Isn't the MT9076 free running when it > > > doesn't see a line-sync? > > > Yes, the MT goes free running when its not sinced. > > But the MT9076 is a module on my hardware. I can mount the backplane > > with or without the MT9076 chip. > > That is the point, what to do when I have the E1 module installed. How > > to interface with it. > > My FPGA is an Spartan 3e S100 (almost 100% full): > > > Logic Utilization: > > Total Number Slice Registers: 737 out of 1,920 38% > > Number used as Flip Flops: 731 > > Number used as Latches: 6 > > Number of 4 input LUTs: 956 out of 1,920 49% > > Logic Distribution: > > Number of occupied Slices: 959 out of > > 960 99% > > Number of Slices containing only related logic: 959 out of > > 959 100% > > Number of Slices containing unrelated logic: 0 out of > > 959 0% > > *See NOTES below for an explanation of the effects of unrelated > > logic > > Total Number of 4 input LUTs: 1,910 out of 1,920 99% > > Number used as logic: 956 > > Number used as a route-thru: 181 > > Number used for Dual Port RAMs: 768 > > (Two LUTs used per Dual Port RAM) > > Number used as Shift registers: 5 > > Number of bonded IOBs: 93 out of 108 86% > > IOB Flip Flops: 19 > > Number of Block RAMs: 4 out of 4 100% > > Number of GCLKs: 9 out of 24 37% > > Number of DCMs: 2 out of 2 100% > > > Another thing. How to reduce the area usage?? > > > Thanks! Hey guys! Thanks for your reply. =) I will explain my problem. I have a internal clock of 16.384MHz (50ppm) and a E1 interface (MT9076B). The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame sync signal, active low). When the E1 is installed (MT9076 chip is soldered at motherboard), I use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I use to send the E1 data to MT9076, aligned with F0 signal. What I want to do is use only the internal 2.048MHz (generate from 16.384MHz clock, with DCM) and interface with E1 through a FIFO. Here is the problem. Internal and external clock are different, so the FIFO will go underflow or overflow... What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 goes free running I will have problem anyway. Waiting suggestions.. =) Thanks!
From: RCIngham on 29 Jan 2010 06:18 [older stuff elided] >I will explain my problem. >I have a internal clock of 16.384MHz (50ppm) and a E1 interface >(MT9076B). >The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame >sync signal, active low). >When the E1 is installed (MT9076 chip is soldered at motherboard), I >use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e >S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I >use to send the E1 data to MT9076, aligned with F0 signal. >What I want to do is use only the internal 2.048MHz (generate from >16.384MHz clock, with DCM) and interface with E1 through a FIFO. >Here is the problem. Internal and external clock are different, so the >FIFO will go underflow or overflow... >What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 >goes free running I will have problem anyway. > >Waiting suggestions.. =3D) > >Thanks! > Ignoring the FPGA implementation issues and concentrating on the system design for a moment: What you want is a local Nx2048kHz clock, which can be slaved to an external 2048kHz clock when it is present (probably by a PLL), but free-runs at the correct nominal frequency when absent. This was quite a common requirement for telecomms equipment about 20 years ago. Thus when there is valid E1 data, none is lost. How to implement this using the inferior clock resources of the Spartan series of FPGAs is a rather harder question, which is left to others... Cheers, Robert --------------------------------------- Posted through http://www.FPGARelated.com
From: rickman on 29 Jan 2010 15:19
On Jan 28, 11:59 am, Morppheu <jdemam...(a)gmail.com> wrote: > On Jan 13, 1:35 pm, rickman <gnu...(a)gmail.com> wrote: > > > > > I'm not sure where this thread started, I don't see a message before > > Nico's post Jan 11. Did you post your code? > > > Your design is using about 10% of the LUTs as routing, which does tend > > to happen when your LUT usage rises using up much of the routing > > resources. The main offender that I can see is the use of almost 50% > > of the LUTs as DP RAM. I am guessing that these are being used for > > FIFO buffers. Can you reduce the number of LUTs used for buffering or > > are they all required? > > > As to the clocking issue, I don't know what the problem is exactly. > > Why can't you use the E1 clock? What pin is the E1 clock connected to > > on the S3 part? I would hope it is connected to a DCM or at least a > > clock input. > > > It is hard to suggest much more without more insight into what your > > design is doing. > > > Rick > > > On Jan 12, 9:00 am, Morppheu <jdemam...(a)gmail.com> wrote:> > Why use the internal clock? Isn't the MT9076 free running when it > > > > doesn't see a line-sync? > > > > Yes, the MT goes free running when its not sinced. > > > But the MT9076 is a module on my hardware. I can mount the backplane > > > with or without the MT9076 chip. > > > That is the point, what to do when I have the E1 module installed. How > > > to interface with it. > > > My FPGA is an Spartan 3e S100 (almost 100% full): > > > > Logic Utilization: > > > Total Number Slice Registers: 737 out of 1,920 38% > > > Number used as Flip Flops: 731 > > > Number used as Latches: 6 > > > Number of 4 input LUTs: 956 out of 1,920 49% > > > Logic Distribution: > > > Number of occupied Slices: 959 out of > > > 960 99% > > > Number of Slices containing only related logic: 959 out of > > > 959 100% > > > Number of Slices containing unrelated logic: 0 out of > > > 959 0% > > > *See NOTES below for an explanation of the effects of unrelated > > > logic > > > Total Number of 4 input LUTs: 1,910 out of 1,920 99% > > > Number used as logic: 956 > > > Number used as a route-thru: 181 > > > Number used for Dual Port RAMs: 768 > > > (Two LUTs used per Dual Port RAM) > > > Number used as Shift registers: 5 > > > Number of bonded IOBs: 93 out of 108 86% > > > IOB Flip Flops: 19 > > > Number of Block RAMs: 4 out of 4 100% > > > Number of GCLKs: 9 out of 24 37% > > > Number of DCMs: 2 out of 2 100% > > > > Another thing. How to reduce the area usage?? > > > > Thanks! > > Hey guys! > Thanks for your reply. =) > I will explain my problem. > I have a internal clock of 16.384MHz (50ppm) and a E1 interface > (MT9076B). > The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame > sync signal, active low). > When the E1 is installed (MT9076 chip is soldered at motherboard), I > use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e > S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I > use to send the E1 data to MT9076, aligned with F0 signal. > What I want to do is use only the internal 2.048MHz (generate from > 16.384MHz clock, with DCM) and interface with E1 through a FIFO. > Here is the problem. Internal and external clock are different, so the > FIFO will go underflow or overflow... > What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 > goes free running I will have problem anyway. > > Waiting suggestions.. =) > > Thanks! I guess I don't understand how things are connected. You seem to have three clocks in the system and I don't know when (or why) you want to use what clock. I understand that the E1 clock at 2.048 MHz is used to clock data from the interface. I think you want to sync the internal 16.384 MHz clock to the E1 so you can process data faster than the 2.048 MHz clock allows. But what is the clock from the MT9076 chip used for? If the MT clock is used to clock data when the E1 clock is not present, you will need to mux the two clocks (E1 and MT) before using them to sync to the internal clock. Does that do the job you are looking for? Rick |