From: Mike Jr on
http://www.slideshare.net/yang/oct2009-2337610

"the operating system would no longer resemble the kernel mode of
today's OSes, but rather act more like a hypervisor. A concept from
virtualization, a hypervisor acts as a layer between the virtual
machine and the actual hardware."

How is Linux planning to up its support for multicore CPU's? Is there
a road map?

--Mike Jr.
From: Peter Köhlmann on
Mike Jr wrote:

> http://www.slideshare.net/yang/oct2009-2337610
>
> "the operating system would no longer resemble the kernel mode of
> today's OSes, but rather act more like a hypervisor. A concept from
> virtualization, a hypervisor acts as a layer between the virtual
> machine and the actual hardware."
>
> How is Linux planning to up its support for multicore CPU's? Is there
> a road map?
>

You mean multicore like the suercomputers running under linux right now?
You know, those with *thousands* of cores?


Do you have even a tiny point?
--
Klingon function calls do not have 'parameters' -
they have 'arguments' - and they ALWAYS WIN THEM.

From: Noob on
Mike Jr wrote:

> How is Linux planning to up its support for multicore CPU's?

Incrementally.

http://www.linux-mag.com/id/6868
http://www.kernel.org/doc/man-pages/online/pages/man7/numa.7.html
http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access
From: Mike Jr on
On Mar 22, 6:54 am, Noob <r...(a)127.0.0.1> wrote:
> Mike Jrwrote:
> > How is Linux planning to up its support for multicore CPU's?
>
> Incrementally.
>
> http://www.linux-mag.com/id/6868http://www.kernel.org/doc/man-pages/online/pages/man7/numa.7.htmlhttp://en.wikipedia.org/wiki/Non-Uniform_Memory_Access

Noob,
Thank you. In the far distant past, IBM had a machine called the SP2
that used a shared nothing architecture to get around the SMP shared
memory bottleneck. The SP2 was a supercomputer.

I have read your references with interest. I have to go to work now
but will get back to them later tonight when I have more time.

BTW, I am posting this from my Ubuntu home computer running on an
Intel i7 multi-core CPU.

--Mike Jr.
From: Anne & Lynn Wheeler on

Mike Jr <n00spam(a)comcast.net> writes:
> Thank you. In the far distant past, IBM had a machine called the SP2
> that used a shared nothing architecture to get around the SMP shared
> memory bottleneck. The SP2 was a supercomputer.

before SP2 ... there was SP1 ... some of the genesis mentioned in this
jan92 meeting in ellison's conference room
http://www.garlic.com/~lynn/95.html#13

and this old email
http://www.garlic.com/~lynn/lhwemail.html#medusa

before it was transferred and positioned as numerical intensive only.

recent thread in c.a.
http://www.garlic.com/~lynn/2010f.html#47 Nonlinear systems and nonlocal supercomputing
http://www.garlic.com/~lynn/2010f.html#48 Nonlinear systems and nonlocal supercomputing
http://www.garlic.com/~lynn/2010f.html#49 Nonlinear systems and nonlocal supercomputing

as mentioned in the above thread ... the reason for doing message
passing was the rios chip set didn't support cache consistency for
shared memory (aka it "scale" past one). the engineering manager that we
reported to when starting the project had only relatively recently moved
to be head of somerset (joint motorola, ibm, apple, etc) that would do
single chip 801/risc and eventually support for cache consistency and
shared memory. as mentioned in the above thread, had also been doing
some stuff with SCI (which was numa shared memory) ... but until had a
chip that cache consistency semantics ... there wasn't much to do.

in any case, within hrs of this email ... the hammer fell, the effort
transferred, we were told we couldn't work on anything with more than
four processors
http://www.garlic.com/~lynn/2006x.html#email920129

it was then announced as product for numerical intensive only ... some
past press ... one from 17feb92
http://www.garlic.com/~lynn/2001n.html#6000clusters

and another from later that summer
http://www.garlic.com/~lynn/2001n.html#6000clusters2

and we were gone within weeks of the above (got paid to leave and not
come back ... extra enducement was structured as sabbatical w/some
benefits to retirement). recent mention getting letter on the
last day claiming was promoted the following day ... this was after a
decade of being told that there were no promotions in my future
http://www.garlic.com/~lynn/2009r.html#6 Have you ever though about taking a sabbatical?
http://www.garlic.com/~lynn/2010f.html#20 Would you fight?

the SCI NUMA (multi-core) flavor from the 90s was multiple (2-4,
single-core) chips on the same board with shared L2 ... that were then
interconnected with SCI. sequent and data general both did four intel
processor boards with SCI & convex did a two hp risc processor boards
(with SCI).

note that some of same the people involved in transferring the project
and telling us that we couldn't work on anything with than four
processors ... had also been involved in blocking our bidding on NSFNET
RFP; a couple recent references (i.e. director of NSF even wrote letter
to company execs ... but that just aggravated the internal politics)
http://www.garlic.com/~lynn/2010e.html#64 LPARs: More or Less?
http://www.garlic.com/~lynn/2010e.html#80 Entry point for a Mainframe?

--
42yrs virtualization experience (since Jan68), online at home since Mar1970