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From: Sudhir Singh on 8 Jun 2010 19:53
Hi Guys,

I am just wondering if there are any standard ways of disabling an ip
core after an evaluation period of say 30 days. I am trying to provide
a potential customer a ip core but don't want them to continue using
it after the eval license period expires. The core will run on Xilinx
Spartan3 FPGAs.

Any suggestions will be much appreciated.

Regards
Sudhir
From: Eric Smith on 8 Jun 2010 20:16
> I am just wondering if there are any standard ways of disabling an ip
> core after an evaluation period of say 30 days.

If the target doesn't have a real time clock, or some other way to
access the time (e.g., an internet connection), then there's no
obvious way to do it.

What Xilinx does for their own evaluation cores is make them stop
working after a certain number of clock cycles from power-up, so that
you can see that it works for a while, but to keep it working, you
have to keep resetting the hardware.
From: glen herrmannsfeldt on 8 Jun 2010 20:18
Sudhir Singh <Sudhir.Singh(a)email.com> wrote:

> I am just wondering if there are any standard ways of disabling an ip
> core after an evaluation period of say 30 days. I am trying to provide
> a potential customer a ip core but don't want them to continue using
> it after the eval license period expires. The core will run on Xilinx
> Spartan3 FPGAs.

Considering the ability to change the date on the computer,
it is pretty hard to stop people from using something past
a given date. Once the bit file is generated, it is pretty
much impossible.

The only ways I can think of would require a response from you.
One possiblility is that you (on your machine) do the actual
synthesis and P&R.

Otherwise, if the license agreement has a large penalty for
using it past 30 days, and you catch them using it...

-- glen
From: Sudhir Singh on 9 Jun 2010 03:07
Hi Eric,
Thanks for your reply. I don't have access to a real time clock so I
guess we'll have to live with having to reset the board.
Cheers
Sudhir



On Jun 9, 12:16 pm, Eric Smith <space...(a)gmail.com> wrote:
> > I am just wondering if there are any standard ways of disabling an ip
> > core after an evaluation period of say 30 days.
>
> If the target doesn't have a real time clock, or some other way to
> access the time (e.g., an internet connection), then there's no
> obvious way to do it.
>
> What Xilinx does for their own evaluation cores is make them stop
> working after a certain number of clock cycles from power-up, so that
> you can see that it works for a while, but to keep it working, you
> have to keep resetting the hardware.

From: Anssi Saari on 9 Jun 2010 12:34
glen herrmannsfeldt <gah(a)ugcs.caltech.edu> writes:

> Sudhir Singh <Sudhir.Singh(a)email.com> wrote:
>
>> I am just wondering if there are any standard ways of disabling an ip
>> core after an evaluation period of say 30 days. I am trying to provide
>> a potential customer a ip core but don't want them to continue using
>> it after the eval license period expires. The core will run on Xilinx
>> Spartan3 FPGAs.
>
> Considering the ability to change the date on the computer,
> it is pretty hard to stop people from using something past
> a given date. Once the bit file is generated, it is pretty
> much impossible.

Well, at least the licensable Xilinx IP I've used included some kind
of timer in the bitfile itself if there's no license, so that the
block works for a few hours and then quits.
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