How to find latches in Xilinx ISE 10.1
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From: RCIngham on 12 Apr 2010 12:14 Greetings, The synthesis report on my design tells me that I have caused 3 latches to be created: 1 LDC and 2 LDP. I didn't intend to create any... Rather frustratingly, the reports aren't telling me which signals are associated with these latches, so that I can fix my code! My colleagues can't remember what the trick is. Please can someone enlighten me? Thanks in advance, R. --------------------------------------- Posted through http://www.FPGARelated.com
From: Symon on 12 Apr 2010 12:33 On 4/12/2010 5:14 PM, RCIngham wrote: > Greetings, > > The synthesis report on my design tells me that I have caused 3 latches to > be created: 1 LDC and 2 LDP. I didn't intend to create any... > > Rather frustratingly, the reports aren't telling me which signals are > associated with these latches, so that I can fix my code! My colleagues > can't remember what the trick is. Please can someone enlighten me? > > Thanks in advance, > R. > Search through the EDIF file? HTH, Syms.
From: RCIngham on 12 Apr 2010 12:59 >On 4/12/2010 5:14 PM, RCIngham wrote: >> Greetings, >> >> The synthesis report on my design tells me that I have caused 3 latches to >> be created: 1 LDC and 2 LDP. I didn't intend to create any... >> >> Rather frustratingly, the reports aren't telling me which signals are >> associated with these latches, so that I can fix my code! My colleagues >> can't remember what the trick is. Please can someone enlighten me? >> >> Thanks in advance, >> R. >> > >Search through the EDIF file? > >HTH, Syms. > What EDIF file? Or perhaps, which EDIF file? And don't suggest the post-Synthesis gate-level netlist, either. Been through that and failed to find and LD* components... --------------------------------------- Posted through http://www.FPGARelated.com
From: backhus on 13 Apr 2010 02:02 On 12 Apr., 18:59, "RCIngham" <robert.ingham(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >On 4/12/2010 5:14 PM, RCIngham wrote: > >> Greetings, > > >> The synthesis report on my design tells me that I have caused 3 latches > to > >> be created: 1 LDC and 2 LDP. I didn't intend to create any... > > >> Rather frustratingly, the reports aren't telling me which signals are > >> associated with these latches, so that I can fix my code! My colleagues > >> can't remember what the trick is. Please can someone enlighten me? > > >> Thanks in advance, > >> R. > > >Search through the EDIF file? > > >HTH, Syms. > > What EDIF file? Or perhaps, which EDIF file? > And don't suggest the post-Synthesis gate-level netlist, either. Been > through that and failed to find and LD* components... > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com Hi, the synthesis report tells you at least in which module of your design the latch is found. The reasons are mostly cases without when others and ifs withut else in combinatorical processes. (or conditional assignments outside of processes) These should be easy to identify. You shouldn't have too many combinatorical processes anyway. Have a nice synthesis Eilert
From: HT-Lab on 13 Apr 2010 03:45
If your design is not to vendor specific you can try QNS to see what it comes back with, Hans www.ht-lab.com "RCIngham" <robert.ingham(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message news:rv-dnR4A5Kl5217WnZ2dnUVZ_qednZ2d(a)giganews.com... > Greetings, > > The synthesis report on my design tells me that I have caused 3 latches to > be created: 1 LDC and 2 LDP. I didn't intend to create any... > > Rather frustratingly, the reports aren't telling me which signals are > associated with these latches, so that I can fix my code! My colleagues > can't remember what the trick is. Please can someone enlighten me? > > Thanks in advance, > R. > > > --------------------------------------- > Posted through http://www.FPGARelated.com |