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From: Paul A. Clayton on 1 Feb 2010 17:34
Would it be useful to make holes through the wafer before
metalization, then fill the holes, then add the metal layers, then
remove the replace the fill material with metal?

Would it be sensible to concentrate on die edges where greater 'slack'
is available for wafer-level processing (given the separation of dies
to accomodate sawing) and the easier access after separation (allowing
etching methods??)?

Would it be appropriate while developing the technology to initially
use large vias for providing power? (Such could perhaps carry more
current per connection than narrower connections on the top and free
more top connections for signalling??)


Paul A. Clayton
just a technophile
From: Del Cecchi on 1 Feb 2010 20:45

"Paul A. Clayton" <paaronclayton(a)embarqmail.com> wrote in message
news:02e5eb6f-712a-4de4-aac5-ef6d67dd5264(a)f11g2000yqm.googlegroups.com...
> Would it be useful to make holes through the wafer before
> metalization, then fill the holes, then add the metal layers, then
> remove the replace the fill material with metal?
>
> Would it be sensible to concentrate on die edges where greater
> 'slack'
> is available for wafer-level processing (given the separation of
> dies
> to accomodate sawing) and the easier access after separation
> (allowing
> etching methods??)?
>
> Would it be appropriate while developing the technology to initially
> use large vias for providing power? (Such could perhaps carry more
> current per connection than narrower connections on the top and free
> more top connections for signalling??)
>
>
> Paul A. Clayton
> just a technophile

where are you going with this? My guess is that most of this stuff
has already been patented for use in stacked chip packaging.

Any via through the wafer would have to be pretty big, even with
thinning techniques.

del


From: Paul A. Clayton on 3 Feb 2010 13:46
On Feb 1, 8:45 pm, "Del Cecchi" <delcec...(a)gmail.com> wrote:
[snip]
> where are you going with this?   My guess is that most of this stuff
> has already been patented for use in stacked chip packaging.

I would not consider such particularly 'non-obvious'--especially
to one skilled in the art.

I was wondering why TSV (and 3D assembly in general) has limited
uptake, particularly when the above ideas seem (to my ignorant
mind) somewhat 'accessible' (easier initial steps), albeit with
limited benefit (allowing a modestly larger number of tradition
connections to be used for data transfer--when using thick TSV
for power/ground--and/or some additional connections for data
transfer--ideally one could double bandwidth, right?)

> Any via through the wafer would have to be pretty big, even with
> thinning techniques.

Which is why I was asking about die-edge (where one has some
slack allowed for later sawing) and thick (die-internal) vias
for power.

By the way, I get the impression that traditional packaging
does not use thicker connections for power/ground. If so, why?
Would the assembly machines be that much more expensive?
(Obviously they would be initially because of low volume, but
in my ignorance it would not seem that such would add that
much complexity.) Or would thicker power/ground connections
be pointless because the limit is not the amount of power
but the distribution of power?

(Thank you Del for your contributions to comp.arch--and
particularly for responding to my post.)


Paul A. Clayton
just a technophile
From: MitchAlsup on 3 Feb 2010 21:17
On Feb 3, 12:46 pm, "Paul A. Clayton" <paaronclay...(a)embarqmail.com>
wrote:
> By the way, I get the impression that traditional packaging
> does not use thicker connections for power/ground.  If so, why?

Depends on what you mean. I have seen packages that have power and
ground planes with thicker copper layers than the signal layers
(sometimes even clocks are routed up here), and I have seen silicon
designs where a lot of the upper layer metalization was used for power
and grounding (and a few critical signals). On the other hand I have
seen the power and ground routes completely intermeshed with the
signal layers to provide more localized current returns and treat the
adjacent wires more like on-die transmission lines. So you question
needs refinement before any reasonable answer can be given.

> Would the assembly machines be that much more expensive?

No, but using two different wire sizes would be expensive. However
this is mostly moot due to flip packaging being de rigeuer anyway.

> Or would thicker power/ground connections
> be pointless because the limit is not the amount of power
> but the distribution of power?

It's both, in addition as the edge speed gets faster than 300 ps, on-
die capacitive decoupling become manditory, so its not the
distribution of power that is important, its the distribution of power
as seen by 10-60 ps current spikes of the bigger gates in the design.
It is simply impossible to decouple these from outside the chip
itself. It is difficult to decouple these inside the die, also.

As to why no through vias--DRAMs use deep vias (trench capacitors),
but realistically to get all the way through the wafer would take at
least a dozen iterations of spin-on-photo; bake, expose, develope,
rinse, etch, wash repeat. If yo mde the vias big enough to fill with
metal for power and ground routes, there would have significant
inductance, and high yield problems due to step coverage on
metalization, groini boundaries, and general control of the metal. If
you started with a via "about" the size of a 'pad' and etched a
triangular via to the bottom you might be able to get the metalization
coverage to deliver power and yield, but at this point you are not
smaller than using it from the front.

I did see a presentation on through silicon vias a decade ago, but the
purpose was to use silicon vias to allow individual nerve fibers to
reconnect after nerve surgury. Had almost nothing to do with chips as
we understand them.

Mitch
From: Del Cecchi on 4 Feb 2010 00:55
MitchAlsup wrote:
> On Feb 3, 12:46 pm, "Paul A. Clayton" <paaronclay...(a)embarqmail.com>
> wrote:
>> By the way, I get the impression that traditional packaging
>> does not use thicker connections for power/ground. If so, why?
>
> Depends on what you mean. I have seen packages that have power and
> ground planes with thicker copper layers than the signal layers
> (sometimes even clocks are routed up here), and I have seen silicon
> designs where a lot of the upper layer metalization was used for power
> and grounding (and a few critical signals). On the other hand I have
> seen the power and ground routes completely intermeshed with the
> signal layers to provide more localized current returns and treat the
> adjacent wires more like on-die transmission lines. So you question
> needs refinement before any reasonable answer can be given.
>
>> Would the assembly machines be that much more expensive?
>
> No, but using two different wire sizes would be expensive. However
> this is mostly moot due to flip packaging being de rigeuer anyway.
>
>> Or would thicker power/ground connections
>> be pointless because the limit is not the amount of power
>> but the distribution of power?
>
> It's both, in addition as the edge speed gets faster than 300 ps, on-
> die capacitive decoupling become manditory, so its not the
> distribution of power that is important, its the distribution of power
> as seen by 10-60 ps current spikes of the bigger gates in the design.
> It is simply impossible to decouple these from outside the chip
> itself. It is difficult to decouple these inside the die, also.
>
> As to why no through vias--DRAMs use deep vias (trench capacitors),
> but realistically to get all the way through the wafer would take at
> least a dozen iterations of spin-on-photo; bake, expose, develope,
> rinse, etch, wash repeat. If yo mde the vias big enough to fill with
> metal for power and ground routes, there would have significant
> inductance, and high yield problems due to step coverage on
> metalization, groini boundaries, and general control of the metal. If
> you started with a via "about" the size of a 'pad' and etched a
> triangular via to the bottom you might be able to get the metalization
> coverage to deliver power and yield, but at this point you are not
> smaller than using it from the front.
>
> I did see a presentation on through silicon vias a decade ago, but the
> purpose was to use silicon vias to allow individual nerve fibers to
> reconnect after nerve surgury. Had almost nothing to do with chips as
> we understand them.
>
> Mitch
If my memory doesn't deceive me, the upper metal levels of some cmos
processes had thicker copper as an option.

The big thing about all the fancy through wafer vias and 3d packaging is
whether or not it produces a benefit that is worth the cost of the
additional processing.

I bet if you searched the patent database of your choice you would come
up with a bunch.
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