Maximum number of operands for x86 and x64 instruction set ?
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From: Ken Hagan on 8 Jun 2010 05:19 On Tue, 08 Jun 2010 02:44:51 +0100, Skybuck Flying <IntoTheFuture(a)hotmail.com> wrote: > Ok, so implicit operands which I would call the hardcoded operands can be > many... > > This leaves the question how many explicit/flexible operands can > instructions have ? > > For now my guess would be 2 for general x86 instructions... for sse I am > not so sure... There's no need to guess, since Intel publish more documentation than you could possibly want on the subject. See http://www.intel.com/products/processor/manuals/index.htm. There are instructions that modify many registers, but the registers involved are always implicit. Generally there are just one or two explicit arguments, and at most one of those can use an addressing mode that involves multiple registers. This follows from the instruction format. x86 instructions are a 1 or 2-byte "op-code" (more recently, but rarely, 3 bytes), which may be followed by a "modrm" byte, which may in turn be followed by a "sib" byte. After those you might have 1, 2 or 4 bytes of immediate data. In front of the whole instruction you might have one or more prefix bytes. That's it. (Since you asked the question, I'm guessing that you were expecting something a little less constrained.) The MMX and SSE instructions aren't any different from the traditional ones in terms of encoding. They do work on different registers, but that's implicit in the op-code. You can't freely mix MMX and SSE registers with normal instructions. It's no accident that there are 8 general purpose registers, 8 FPU registers, 8 MMX registers and 8 SSE registers. They are all shoe-horned into the same instruction format.
From: Noob on 8 Jun 2010 07:49 Ken Hagan wrote: > There are instructions that modify many registers, but the registers > involved are always implicit. Generally there are just one or two > explicit arguments, and at most one of those can use an addressing mode > that involves multiple registers. This follows from the instruction format. AFAIU, AVX will introduce 3-operand instructions. http://en.wikipedia.org/wiki/Advanced_Vector_Extensions http://en.wikipedia.org/wiki/VEX_prefix http://software.intel.com/en-us/articles/intel-avx-new-frontiers-in-performance-improvements-and-energy-efficiency/ Regards.
From: Michael S on 8 Jun 2010 20:21 On Jun 8, 3:44 am, "Skybuck Flying" <IntoTheFut...(a)hotmail.com> wrote: > Ok, so implicit operands which I would call the hardcoded operands can be > many... > > This leaves the question how many explicit/flexible operands can > instructions have ? > > For now my guess would be 2 for general x86 instructions... Assuming, by 'operands' you meant "register operands" the answer is 3 (LEA). If you also count immediate operands than LEA gets up to 4 and IMUL up to 3. For the rest of general-purpose non-memory instruction - 2. > for sse I am not so sure... For majority of SSE instruction - two. For some (e.g. shuffles) two + one immediate. SSE4.1 BLENDVPx instructions have three register operands but one of the inputs always comes from XMM0. For coming AVX extension - three. > > Bye, > Skybuck.
From: Ken Hagan on 9 Jun 2010 05:03 On Tue, 08 Jun 2010 12:49:02 +0100, Noob <root(a)127.0.0.1> wrote: > http://en.wikipedia.org/wiki/Advanced_Vector_Extensions > http://en.wikipedia.org/wiki/VEX_prefix > http://software.intel.com/en-us/articles/intel-avx-new-frontiers-in-performance-improvements-and-energy-efficiency/ Gosh. It's like RISC never happened.
From: MitchAlsup on 10 Jun 2010 10:24
On Jun 9, 4:03 am, "Ken Hagan" <K.Ha...(a)thermoteknix.com> wrote: > On Tue, 08 Jun 2010 12:49:02 +0100, Noob <r...(a)127.0.0.1> wrote: > >http://en.wikipedia.org/wiki/Advanced_Vector_Extensions > >http://en.wikipedia.org/wiki/VEX_prefix > >http://software.intel.com/en-us/articles/intel-avx-new-frontiers-in-p... > > Gosh. It's like RISC never happened. At best, the designers of today remember none of the lessons from that era. Mitch |