From: Randy Yates on
Hi Michael,

Your points are well-taken. Thank you very much for your input and


Michael S <already5chosen(a)> writes:

> On Mar 29, 2:33 am, Randy Yates <ya...(a)> wrote:
>> Michael S <already5cho...(a)> writes:
>> > On Mar 28, 9:27 pm, Symon <symon_bre...(a)> wrote:
>> >> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...(a)> wrote:
>> >> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
>> >> >> that already has a high (baseband) sample rate - around 40-80 MHz.
>> >> > That's a very bad idea.
>> >> > For your sort of application homemade delta-sigma DAC can't match
>> >> > combination of price, SNR, SFDR and power provided by something like
>> >> > AD9754.
>> >> I'm pretty sure on price and power (I assume efficiency?) his solution
>> >> does match your suggested alternative given that, from details in his
>> >> previous postings on this newsgroup, the FPGA/CPLD device is a sunk
>> >> cost. I agree with your other acronyms though!
>> >> Cheers, Syms.
>> > At what rate do you have to generate pulses to build, say 12-bit 80
>> > MSPS? I don't know the exact answer but pretty sure that the required
>> > rate is way above capabilities of CPLDs and likely above what's
>> > possible with smallest FPGAs.
>> > You would need FPGA with the serializer implemented in hardware So,
>> > still on the digital side, you are pushed from something like $4 up to
>> > something like $30 or more. The difference already pays for several
>> > AD9754s both in money and in power consumption. Now, consider all the
>> > analog parts that you need to filter you pulse train into nice analog
>> > signal. Since, even with mid-range FPGA you will have relatively
>> > modest oversampling (factor of 15 or something like that) the analog
>> > filter will have to be rather sharp and probably high order. It would
>> > cost you more money and more power.
>> > As I said above, implementing high speed DAC in programmable logic
>> > device is very bad idea.
>> > Implementing voice-grade (voice, not audio) DAC sounds less crazy but
>> > from point of view of economics, power and board real estate even that
>> > is more often than not a losing proposition.
>> Michael,
>> "Bad" is relative to your criteria. Hint: in my application, cost and
>> power are not important. Size is very important. The AD9754 is 700 mils
>> long, not a small part, and you'd need two of them.
> Not as small part in SOIC, but pretty small in TSSO packet. Anyway,
> AD9754 is just an example of the sort of external DAC we compare
> against. For practical IQ application you are likely to pick AD9116/
> AD9117. And don't forget the analog components required by delta-sigma
> take space too.
> However if the power and cost is less important but the size is
> paramount, may be, direct conversion to IF with really fast DAC is a
> better idea?
>> But I do agree it is not a good idea unless you really need it.
>> By the way, I have designed a production-quality delta sigma D/A. It
>> went in over 17M Sony Ericsson phones. But it was implemented in
>> software on a TMS320C54x, not FPGA. You can see a presentation I
>> made on it at the first comp.dsp conference here:
> It's not clear from presentation but I suppose that you are talking
> about voice-grade DAC or may be something a little worse than the
> classic 100 to 3200 Hz voice grade that was considered acceptable in
> 10 y.o. wireless phones.
> Not much of relationship with bandwidth and phase linearity
> requirements of 20 Mbps QPSK transmitter.
>> --
>> Randy Yates % "I met someone who looks alot like you,
>> Digital Signal Labs % she does the things you do,
>> mailto://ya...(a) % but she is an IBM." 'Yours Truly, 2095', *Time*, ELO

Randy Yates % "The dreamer, the unwoken fool -
Digital Signal Labs % in dreams, no pain will kiss the brow..."
mailto://yates(a) % % 'Eldorado Overture', *Eldorado*, ELO