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From: Randy Yates on 28 Mar 2010 08:31
I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
that already has a high (baseband) sample rate - around 40-80 MHz.

What kind of (single-bit) output rate can you get with a CPLD or FPGA
device?
--
Randy Yates % "Remember the good old 1980's, when
Digital Signal Labs % things were so uncomplicated?"
mailto://yates(a)ieee.org % 'Ticket To The Moon'
http://www.digitalsignallabs.com % *Time*, Electric Light Orchestra
From: Symon on 28 Mar 2010 10:25
On 3/28/2010 1:31 PM, Randy Yates wrote:
> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
> that already has a high (baseband) sample rate - around 40-80 MHz.
>
> What kind of (single-bit) output rate can you get with a CPLD or FPGA
> device?

Hi Randy,
You should read the datasheets, or narrow down exactly want you want.
There are many different types of output on these parts. Your question
is like, "I want to drive from "A" to "B". How fast can a car or
motorcycle go?".
HTH, Syms.

p.s. >200Mbps for single ended CMOS outputs. ;-)


From: Phil Jessop on 28 Mar 2010 11:21

"Symon" <symon_brewer(a)hotmail.com> wrote in message
news:honos0$dkk$1(a)news.eternal-september.org...
> On 3/28/2010 1:31 PM, Randy Yates wrote:
>> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
>> that already has a high (baseband) sample rate - around 40-80 MHz.
>>
>> What kind of (single-bit) output rate can you get with a CPLD or FPGA
>> device?
>
> Hi Randy,
> You should read the datasheets, or narrow down exactly want you want.
> There are many different types of output on these parts. Your question is
> like, "I want to drive from "A" to "B". How fast can a car or motorcycle
> go?".
> HTH, Syms.
>
> p.s. >200Mbps for single ended CMOS outputs. ;-)
>
>

11.3Gbps on Stratix IV GT PCML outputs


From: Michael S on 28 Mar 2010 12:51
On Mar 28, 2:31 pm, Randy Yates <ya...(a)ieee.org> wrote:
> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
> that already has a high (baseband) sample rate - around 40-80 MHz.
>

That's a very bad idea.
For your sort of application homemade delta-sigma DAC can't match
combination of price, SNR, SFDR and power provided by something like
AD9754.


> What kind of (single-bit) output rate can you get with a CPLD or FPGA
> device?
> --
> Randy Yates                      % "Remember the good old 1980's, when
> Digital Signal Labs              %  things were so uncomplicated?"
> mailto://ya...(a)ieee.org          % 'Ticket To The Moon'http://www.digitalsignallabs.com% *Time*, Electric Light Orchestra

From: Symon on 28 Mar 2010 15:27
On 3/28/2010 5:51 PM, Michael S wrote:
> On Mar 28, 2:31 pm, Randy Yates<ya...(a)ieee.org> wrote:
>> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
>> that already has a high (baseband) sample rate - around 40-80 MHz.
>>
>
> That's a very bad idea.
> For your sort of application homemade delta-sigma DAC can't match
> combination of price, SNR, SFDR and power provided by something like
> AD9754.
>
I'm pretty sure on price and power (I assume efficiency?) his solution
does match your suggested alternative given that, from details in his
previous postings on this newsgroup, the FPGA/CPLD device is a sunk
cost. I agree with your other acronyms though!
Cheers, Syms.
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