From: Antti on 21 Dec 2009 04:17
I hope my plea will not be seen as usual "please help me" request. I
do my (home)work, I try hard but sometimes there come up problems that
seem very hard to solve, with the current problem, well if there is no
solution to that, then I wonder how come it has been ever been
possible to use Xilinx FIFO's with problem at all? So the problem:
Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY
signals at input correct, as expected (checked with ChipScope)
signals at output:
- double value
- missing 1, 2 or 3 values
- FIFO will read out random number of OLD entries, this could be 4
values, or 50% of the FIFO old values
I can select BRAM or FIFO16 implementation in Coregen, it doesnt
change the problem
Virtex-4, ISE 10.1SP3
Please help me, if anyone has some good suggestion (except use Altera
advice), I am getting really desperate. To the extent that when i
friend called my yesterday, then after my "hello", his first response
was: "Are you dead?". I had to explain that i am not.
From: Jon Beniston on 21 Dec 2009 04:40
> Virtex-4, FIFOs
I thought I read there was a bug in those...
From: Antti on 21 Dec 2009 05:05
On Dec 21, 11:40 am, Jon Beniston <j...(a)beniston.com> wrote:
> > Virtex-4, FIFOs
> I thought I read there was a bug in those...
Well there is a bug in the V4 FIFO16 hard-fifo, but Coregen says that
it DOES APPLY PATCH to fix it.
So I assumed that the FIFO's generated by Coregen do actually work,
but it seems i was wrong :(
From: maxascent on 21 Dec 2009 05:07
Why dont you just write your own fifo? It shouldnt take that long and at
least you would know it was 100% ok.
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From: Antti on 21 Dec 2009 05:12
On Dec 21, 12:07 pm, "maxascent" <maxasc...(a)yahoo.co.uk> wrote:
> Why dont you just write your own fifo? It shouldnt take that long and at
> least you would know it was 100% ok.
Yeah, that advice I have myself ready :) well, I would most likely not
but make dual port RAM instead. Thing is that the system works, the
works, except that "small Xilinx FIFO problem" .. so if there is at
to FIX Xilinx FIFO and to make it WORK then it would made the system
without the need of rewriting HDL or C code