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From: Florian on 10 Dec 2009 04:52
On Dec 9, 9:09 pm, Bob <rsg.ucli...(a)gmail.com> wrote:
> On Dec 9, 1:26 pm, "MM" <mb...(a)yahoo.com> wrote:
>
> > > I'm starting to wonder about how the PHY is reset.  I don't have any
> > > physical access to that signal, so I cannot view it on a scope.  But
> > > the PHY data sheet states it must be at least 10 ms long, and remain
> > > active for at least 10 clock cycles.  Could that be different?
>
> > I believe I measured this at some point in the past and found that it was
> > much much shorter and did not meet the spec of my PHY. However, the PHY I am
> > using doesn't seem to care... On the other hand I remember having a problem
> > similar to yours when TRST pin of the PHY wasn't grounded.
>
> > /Mikhail
>
> After my last email, I decided to control the reset line myself, and
> unfortunately, no improvement.
>
> Then, on a tip, I tried V3.00.a (instead of V3.00.b) of the hard_temac
> IP, and the reading improved dramatically.  At first, I thought it was
> fixed, but looking real close, I noticed there were still a few bit
> errors.
>
> However, it occurred to me that, because I only need to modify two
> registers after reset, and they are both well-defined, I didn't
> actually need to read them.  Once I get past the reset, I have no need
> for any interaction with the PHY's registers.  So, I modified my code
> thusly, and lo and behold, it works!  So at this point, I am happy...
>
> Thanks for the insight, Mikhail!
>
> -Bob

Hi Bob,

a long time ago I inserted a FF between MDIO input and the HARD_TEMAC
clocked with falling MDC.
The 88E1111 is very fast changing the MDIO after the rising MDC and I
don't know when the HARD_TEMAC samples the signal.

Have fun
Florian

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