From: lomtikster on 10 Nov 2008 05:45 Hi, I am facing an issue of accessing the registers of a peripheral sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBlaze is on the PLB bus. The bridge is a slave on PLB and a master on DCR. Please see below for a snippet of the .mhs file. Since my peripheral has the C_DCR_BASEADDR = 0b0000000000, I assume it is register 0 on the PLB2DCR bridge and I can simply access it by looking at the base address of the PLB2DCR. For example, write_adress (0x87000000, value1) write_adress (0x87000004, value2) Does it make sense? BEGIN plbv46_dcr_bridge PARAMETER INSTANCE = plbv46_dcr_bridge_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x87000000 PARAMETER C_HIGHADDR = 0x8700ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MDCR = dcr_v29_0 END BEGIN xps_tft PARAMETER INSTANCE = xps_tft_0 PARAMETER HW_VER = 1.00.a PARAMETER C_DCR_SPLB_SLAVE_IF = 0 PARAMETER C_TFT_INTERFACE = 0 PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 PARAMETER C_DCR_BASEADDR = 0b0000000000 PARAMETER C_DCR_HIGHADDR = 0b0000000011 BUS_INTERFACE MPLB = mb_plb BUS_INTERFACE SDCR = dcr_v29_0 PORT TFT_VSYNC = VGA_VSYNCH PORT TFT_HSYNC = VGA_HSYNCH PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK PORT SYS_TFT_Clk = tft_clk PORT TFT_DE = VGA_OUT_BLANK_Z PORT DCR_Rst = sys_bus_reset PORT DCR_Clk = sys_clk_s PORT TFT_VGA_R = VGA_OUT_RED PORT TFT_VGA_G = VGA_OUT_GREEN PORT TFT_VGA_B = VGA_OUT_BLUE END Thank you in advance
From: sundar on 11 Nov 2008 04:16 On Nov 10, 3:45 pm, lomtiks...(a)gmail.com wrote: > Hi, > > I am facing an issue of accessing the registers of a peripheral > sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBlaze > is on the PLB bus. The bridge is a slave on PLB and a master on DCR. > Please see below for a snippet of the .mhs file. > > Since my peripheral has the C_DCR_BASEADDR = 0b0000000000, I assume it > is register 0 on the PLB2DCR bridge and I can simply access it by > looking at the base address of the PLB2DCR. For example, > write_adress (0x87000000, value1) > write_adress (0x87000004, value2) > Does it make sense? > > BEGIN plbv46_dcr_bridge > PARAMETER INSTANCE = plbv46_dcr_bridge_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_BASEADDR = 0x87000000 > PARAMETER C_HIGHADDR = 0x8700ffff > BUS_INTERFACE SPLB = mb_plb > BUS_INTERFACE MDCR = dcr_v29_0 > END > > BEGIN xps_tft > PARAMETER INSTANCE = xps_tft_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_DCR_SPLB_SLAVE_IF = 0 > PARAMETER C_TFT_INTERFACE = 0 > PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 > PARAMETER C_DCR_BASEADDR = 0b0000000000 > PARAMETER C_DCR_HIGHADDR = 0b0000000011 > BUS_INTERFACE MPLB = mb_plb > BUS_INTERFACE SDCR = dcr_v29_0 > PORT TFT_VSYNC = VGA_VSYNCH > PORT TFT_HSYNC = VGA_HSYNCH > PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK > PORT SYS_TFT_Clk = tft_clk > PORT TFT_DE = VGA_OUT_BLANK_Z > PORT DCR_Rst = sys_bus_reset > PORT DCR_Clk = sys_clk_s > PORT TFT_VGA_R = VGA_OUT_RED > PORT TFT_VGA_G = VGA_OUT_GREEN > PORT TFT_VGA_B = VGA_OUT_BLUE > END > > Thank you in advance Hi, I am not sure how your other EDK setup files looks like but still thot of sharing some info. Note: PLB can be configured as 32,63 or 128 dwidth and address access is by default 32. DCR address access is 10 width so please study address translation section of the Product spec. Now coming to direct query ....the bridge core has registers classified as slave access registers,interrupt registers. I think slave access register may not start from 0. In this case DCR is slave so make sure you are setting proper reg address space. Hope this helps. Sundar
From: lomtikster on 11 Nov 2008 07:34 On Nov 11, 1:16 am, sundar <sundar....(a)gmail.com> wrote: > On Nov 10, 3:45 pm, lomtiks...(a)gmail.com wrote: > > > > > Hi, > > > I am facing an issue of accessing the registers of a peripheral > > sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBlaze > > is on the PLB bus. The bridge is a slave on PLB and a master on DCR. > > Please see below for a snippet of the .mhs file. > > > Since my peripheral has the C_DCR_BASEADDR = 0b0000000000, I assume it > > is register 0 on the PLB2DCR bridge and I can simply access it by > > looking at the base address of the PLB2DCR. For example, > > write_adress (0x87000000, value1) > > write_adress (0x87000004, value2) > > Does it make sense? > > > BEGIN plbv46_dcr_bridge > > PARAMETER INSTANCE = plbv46_dcr_bridge_0 > > PARAMETER HW_VER = 1.00.a > > PARAMETER C_BASEADDR = 0x87000000 > > PARAMETER C_HIGHADDR = 0x8700ffff > > BUS_INTERFACE SPLB = mb_plb > > BUS_INTERFACE MDCR = dcr_v29_0 > > END > > > BEGIN xps_tft > > PARAMETER INSTANCE = xps_tft_0 > > PARAMETER HW_VER = 1.00.a > > PARAMETER C_DCR_SPLB_SLAVE_IF = 0 > > PARAMETER C_TFT_INTERFACE = 0 > > PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 > > PARAMETER C_DCR_BASEADDR = 0b0000000000 > > PARAMETER C_DCR_HIGHADDR = 0b0000000011 > > BUS_INTERFACE MPLB = mb_plb > > BUS_INTERFACE SDCR = dcr_v29_0 > > PORT TFT_VSYNC = VGA_VSYNCH > > PORT TFT_HSYNC = VGA_HSYNCH > > PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK > > PORT SYS_TFT_Clk = tft_clk > > PORT TFT_DE = VGA_OUT_BLANK_Z > > PORT DCR_Rst = sys_bus_reset > > PORT DCR_Clk = sys_clk_s > > PORT TFT_VGA_R = VGA_OUT_RED > > PORT TFT_VGA_G = VGA_OUT_GREEN > > PORT TFT_VGA_B = VGA_OUT_BLUE > > END > > > Thank you in advance > > Hi, > > I am not sure how your other EDK setup files looks like but still thot > of sharing some info. > Note: PLB can be configured as 32,63 or 128 dwidth and address access > is by default 32. > DCR address access is 10 width so please study address translation > section of the Product spec. > Now coming to direct query ....the bridge core has registers > classified as slave access registers,interrupt registers. > I think slave access register may not start from 0. In this case DCR > is slave so make sure you are setting proper reg address space. > > Hope this helps. > > Sundar Thanks for your comments, Sundar. Following your advice, I've searched for slave access registers in plb2dcr bridge and tft controller and have not found the restrictions. There is a restriction for tft connected as slave on the plb bus, but from the eng doc it looks like it is an option for PPC only. I am using microblaze. In any case, I changed C_DCR_BASEADDR of tft controller peripheral to from 0b0010000000 to 0b0010000011 as one of the "ml401_emb_ref_71\projects\ml401_emb_ref" examples I found for ml401 board (it also uses microblaze, but opb2dcr bridge and tft on the dcr as a slave). Still I cannot change the register setting which is supposed to change the frame buffer pointer of the tft. Note that TFT is working fine for the default address that gets programmed with the bitstream (I can see the picture, but I cannot change to another memory location). 2. So, to debug it further, I realized that I might have misconnected the ports on my peripheral. Previously, the xps_tft's DCR_Rst and DCR_Clk were connected to my 100MHz sys_bus_reset and sys_clk_s respectively and plb2dcr_bridge's PLB_dcrRst and PLB_dcrClk-- unconnected. So now, I connected these together because from the eng doc it looks like the PLB's clock has to clock the DCR via BUS2IP_Clk of the bridge. So my mhs file is as below now, but still I cannot access the registers. BEGIN xps_tft PARAMETER INSTANCE = xps_tft_0 PARAMETER HW_VER = 1.00.a PARAMETER C_DCR_SPLB_SLAVE_IF = 0 PARAMETER C_TFT_INTERFACE = 0 PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 PARAMETER C_DCR_BASEADDR = 0b0010000000 <----------changed from 0b0000000000 PARAMETER C_DCR_HIGHADDR = 0b0010000011 <----------changed from 0b0000000011 BUS_INTERFACE MPLB = mb_plb BUS_INTERFACE SDCR = dcr_v29_0 PORT TFT_VSYNC = VGA_VSYNCH PORT TFT_HSYNC = VGA_HSYNCH PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK PORT SYS_TFT_Clk = tft_clk PORT TFT_DE = VGA_OUT_BLANK_Z PORT DCR_Rst = PLB_TO_DCR_RST PORT DCR_Clk = PLB_TO_DCR_CLK PORT TFT_VGA_R = VGA_OUT_RED PORT TFT_VGA_G = VGA_OUT_GREEN PORT TFT_VGA_B = VGA_OUT_BLUE END BEGIN plbv46_dcr_bridge PARAMETER INSTANCE = plbv46_dcr_bridge_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x87000000 PARAMETER C_HIGHADDR = 0x8700ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MDCR = dcr_v29_0 PORT PLB_dcrClk = PLB_TO_DCR_CLK <------------- new connection PORT PLB_dcrRst = PLB_TO_DCR_RST <------------- new connection END 3. I tried reading the memory directly from XMD and got "Debug memory access check failed. Section, 0x87000200-0x8700203 not accessible from processor debug interface. I used 0x87000200 because DCR's offset is 128 (C_DCR_BASEADDR = 0b0010000000) and to translate to PLB format, I multiplied by 4 as suggested. However, I also tried other values including 0x87000080, 0x87000100, 0x87000400, 0x87000800, 0x87001000, etc). Same result. It looks like the address is either not decodable or not accessible due to misconnected ports. What do you think?
From: lomtikster on 11 Nov 2008 21:18 On Nov 11, 4:34 am, lomtiks...(a)gmail.com wrote: > On Nov 11, 1:16 am, sundar <sundar....(a)gmail.com> wrote: > > > > > On Nov 10, 3:45 pm, lomtiks...(a)gmail.com wrote: > > > > Hi, > > > > I am facing an issue of accessing the registers of a peripheral > > > sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBlaze > > > is on the PLB bus. The bridge is a slave on PLB and a master on DCR. > > > Please see below for a snippet of the .mhs file. > > > > Since my peripheral has the C_DCR_BASEADDR = 0b0000000000, I assume it > > > is register 0 on the PLB2DCR bridge and I can simply access it by > > > looking at the base address of the PLB2DCR. For example, > > > write_adress (0x87000000, value1) > > > write_adress (0x87000004, value2) > > > Does it make sense? > > > > BEGIN plbv46_dcr_bridge > > > PARAMETER INSTANCE = plbv46_dcr_bridge_0 > > > PARAMETER HW_VER = 1.00.a > > > PARAMETER C_BASEADDR = 0x87000000 > > > PARAMETER C_HIGHADDR = 0x8700ffff > > > BUS_INTERFACE SPLB = mb_plb > > > BUS_INTERFACE MDCR = dcr_v29_0 > > > END > > > > BEGIN xps_tft > > > PARAMETER INSTANCE = xps_tft_0 > > > PARAMETER HW_VER = 1.00.a > > > PARAMETER C_DCR_SPLB_SLAVE_IF = 0 > > > PARAMETER C_TFT_INTERFACE = 0 > > > PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 > > > PARAMETER C_DCR_BASEADDR = 0b0000000000 > > > PARAMETER C_DCR_HIGHADDR = 0b0000000011 > > > BUS_INTERFACE MPLB = mb_plb > > > BUS_INTERFACE SDCR = dcr_v29_0 > > > PORT TFT_VSYNC = VGA_VSYNCH > > > PORT TFT_HSYNC = VGA_HSYNCH > > > PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK > > > PORT SYS_TFT_Clk = tft_clk > > > PORT TFT_DE = VGA_OUT_BLANK_Z > > > PORT DCR_Rst = sys_bus_reset > > > PORT DCR_Clk = sys_clk_s > > > PORT TFT_VGA_R = VGA_OUT_RED > > > PORT TFT_VGA_G = VGA_OUT_GREEN > > > PORT TFT_VGA_B = VGA_OUT_BLUE > > > END > > > > Thank you in advance > > > Hi, > > > I am not sure how your other EDK setup files looks like but still thot > > of sharing some info. > > Note: PLB can be configured as 32,63 or 128 dwidth and address access > > is by default 32. > > DCR address access is 10 width so please study address translation > > section of the Product spec. > > Now coming to direct query ....the bridge core has registers > > classified as slave access registers,interrupt registers. > > I think slave access register may not start from 0. In this case DCR > > is slave so make sure you are setting proper reg address space. > > > Hope this helps. > > > Sundar > > Thanks for your comments, Sundar. > > Following your advice, I've searched for slave access registers in > plb2dcr bridge and tft controller and have not found the restrictions. > There is a restriction for tft connected as slave on the plb bus, but > from the eng doc it looks like it is an option for PPC only. I am > using microblaze. In any case, I changed C_DCR_BASEADDR of tft > controller peripheral to from 0b0010000000 to 0b0010000011 as one of > the "ml401_emb_ref_71\projects\ml401_emb_ref" examples I found for > ml401 board (it also uses microblaze, but opb2dcr bridge and tft on > the dcr as a slave). Still I cannot change the register setting which > is supposed to change the frame buffer pointer of the tft. Note that > TFT is working fine for the default address that gets programmed with > the bitstream (I can see the picture, but I cannot change to another > memory location). > > 2. So, to debug it further, I realized that I might have misconnected > the ports on my peripheral. Previously, the xps_tft's DCR_Rst and > DCR_Clk were connected to my 100MHz sys_bus_reset and sys_clk_s > respectively and plb2dcr_bridge's PLB_dcrRst and PLB_dcrClk-- > unconnected. So now, I connected these together because from the eng > doc it looks like the PLB's clock has to clock the DCR via BUS2IP_Clk > of the bridge. So my mhs file is as below now, but still I cannot > access the registers. > BEGIN xps_tft > PARAMETER INSTANCE = xps_tft_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_DCR_SPLB_SLAVE_IF = 0 > PARAMETER C_TFT_INTERFACE = 0 > PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 > PARAMETER C_DCR_BASEADDR = 0b0010000000 <----------changed from > 0b0000000000 > PARAMETER C_DCR_HIGHADDR = 0b0010000011 <----------changed from > 0b0000000011 > BUS_INTERFACE MPLB = mb_plb > BUS_INTERFACE SDCR = dcr_v29_0 > PORT TFT_VSYNC = VGA_VSYNCH > PORT TFT_HSYNC = VGA_HSYNCH > PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK > PORT SYS_TFT_Clk = tft_clk > PORT TFT_DE = VGA_OUT_BLANK_Z > PORT DCR_Rst = PLB_TO_DCR_RST > PORT DCR_Clk = PLB_TO_DCR_CLK > PORT TFT_VGA_R = VGA_OUT_RED > PORT TFT_VGA_G = VGA_OUT_GREEN > PORT TFT_VGA_B = VGA_OUT_BLUE > END > > BEGIN plbv46_dcr_bridge > PARAMETER INSTANCE = plbv46_dcr_bridge_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_BASEADDR = 0x87000000 > PARAMETER C_HIGHADDR = 0x8700ffff > BUS_INTERFACE SPLB = mb_plb > BUS_INTERFACE MDCR = dcr_v29_0 > PORT PLB_dcrClk = PLB_TO_DCR_CLK <------------- new connection > PORT PLB_dcrRst = PLB_TO_DCR_RST <------------- new connection > END > > 3. I tried reading the memory directly from XMD and got "Debug memory > access check failed. Section, 0x87000200-0x8700203 not accessible from > processor debug interface. > I used 0x87000200 because DCR's offset is 128 (C_DCR_BASEADDR = > 0b0010000000) and to translate to PLB format, I multiplied by 4 as > suggested. However, I also tried other values including 0x87000080, > 0x87000100, 0x87000400, 0x87000800, 0x87001000, etc). Same result. > > It looks like the address is either not decodable or not accessible > due to misconnected ports. What do you think? If you know of any example that is using the plb to dcr bridge with microblaze, that would be very useful too. I've found only for ML401 board with opb to dcr bridge, but something is still incorrect
From: lomtikster on 12 Nov 2008 01:57 On Nov 11, 4:34 am, lomtiks...(a)gmail.com wrote: > On Nov 11, 1:16 am, sundar <sundar....(a)gmail.com> wrote: > > > > > On Nov 10, 3:45 pm, lomtiks...(a)gmail.com wrote: > > > > Hi, > > > > I am facing an issue of accessing the registers of a peripheral > > > sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBlaze > > > is on the PLB bus. The bridge is a slave on PLB and a master on DCR. > > > Please see below for a snippet of the .mhs file. > > > > Since my peripheral has the C_DCR_BASEADDR = 0b0000000000, I assume it > > > is register 0 on the PLB2DCR bridge and I can simply access it by > > > looking at the base address of the PLB2DCR. For example, > > > write_adress (0x87000000, value1) > > > write_adress (0x87000004, value2) > > > Does it make sense? > > > > BEGIN plbv46_dcr_bridge > > > PARAMETER INSTANCE = plbv46_dcr_bridge_0 > > > PARAMETER HW_VER = 1.00.a > > > PARAMETER C_BASEADDR = 0x87000000 > > > PARAMETER C_HIGHADDR = 0x8700ffff > > > BUS_INTERFACE SPLB = mb_plb > > > BUS_INTERFACE MDCR = dcr_v29_0 > > > END > > > > BEGIN xps_tft > > > PARAMETER INSTANCE = xps_tft_0 > > > PARAMETER HW_VER = 1.00.a > > > PARAMETER C_DCR_SPLB_SLAVE_IF = 0 > > > PARAMETER C_TFT_INTERFACE = 0 > > > PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 > > > PARAMETER C_DCR_BASEADDR = 0b0000000000 > > > PARAMETER C_DCR_HIGHADDR = 0b0000000011 > > > BUS_INTERFACE MPLB = mb_plb > > > BUS_INTERFACE SDCR = dcr_v29_0 > > > PORT TFT_VSYNC = VGA_VSYNCH > > > PORT TFT_HSYNC = VGA_HSYNCH > > > PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK > > > PORT SYS_TFT_Clk = tft_clk > > > PORT TFT_DE = VGA_OUT_BLANK_Z > > > PORT DCR_Rst = sys_bus_reset > > > PORT DCR_Clk = sys_clk_s > > > PORT TFT_VGA_R = VGA_OUT_RED > > > PORT TFT_VGA_G = VGA_OUT_GREEN > > > PORT TFT_VGA_B = VGA_OUT_BLUE > > > END > > > > Thank you in advance > > > Hi, > > > I am not sure how your other EDK setup files looks like but still thot > > of sharing some info. > > Note: PLB can be configured as 32,63 or 128 dwidth and address access > > is by default 32. > > DCR address access is 10 width so please study address translation > > section of the Product spec. > > Now coming to direct query ....the bridge core has registers > > classified as slave access registers,interrupt registers. > > I think slave access register may not start from 0. In this case DCR > > is slave so make sure you are setting proper reg address space. > > > Hope this helps. > > > Sundar > > Thanks for your comments, Sundar. > > Following your advice, I've searched for slave access registers in > plb2dcr bridge and tft controller and have not found the restrictions. > There is a restriction for tft connected as slave on the plb bus, but > from the eng doc it looks like it is an option for PPC only. I am > using microblaze. In any case, I changed C_DCR_BASEADDR of tft > controller peripheral to from 0b0010000000 to 0b0010000011 as one of > the "ml401_emb_ref_71\projects\ml401_emb_ref" examples I found for > ml401 board (it also uses microblaze, but opb2dcr bridge and tft on > the dcr as a slave). Still I cannot change the register setting which > is supposed to change the frame buffer pointer of the tft. Note that > TFT is working fine for the default address that gets programmed with > the bitstream (I can see the picture, but I cannot change to another > memory location). > > 2. So, to debug it further, I realized that I might have misconnected > the ports on my peripheral. Previously, the xps_tft's DCR_Rst and > DCR_Clk were connected to my 100MHz sys_bus_reset and sys_clk_s > respectively and plb2dcr_bridge's PLB_dcrRst and PLB_dcrClk-- > unconnected. So now, I connected these together because from the eng > doc it looks like the PLB's clock has to clock the DCR via BUS2IP_Clk > of the bridge. So my mhs file is as below now, but still I cannot > access the registers. > BEGIN xps_tft > PARAMETER INSTANCE = xps_tft_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_DCR_SPLB_SLAVE_IF = 0 > PARAMETER C_TFT_INTERFACE = 0 > PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10800000 > PARAMETER C_DCR_BASEADDR = 0b0010000000 <----------changed from > 0b0000000000 > PARAMETER C_DCR_HIGHADDR = 0b0010000011 <----------changed from > 0b0000000011 > BUS_INTERFACE MPLB = mb_plb > BUS_INTERFACE SDCR = dcr_v29_0 > PORT TFT_VSYNC = VGA_VSYNCH > PORT TFT_HSYNC = VGA_HSYNCH > PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK > PORT SYS_TFT_Clk = tft_clk > PORT TFT_DE = VGA_OUT_BLANK_Z > PORT DCR_Rst = PLB_TO_DCR_RST > PORT DCR_Clk = PLB_TO_DCR_CLK > PORT TFT_VGA_R = VGA_OUT_RED > PORT TFT_VGA_G = VGA_OUT_GREEN > PORT TFT_VGA_B = VGA_OUT_BLUE > END > > BEGIN plbv46_dcr_bridge > PARAMETER INSTANCE = plbv46_dcr_bridge_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_BASEADDR = 0x87000000 > PARAMETER C_HIGHADDR = 0x8700ffff > BUS_INTERFACE SPLB = mb_plb > BUS_INTERFACE MDCR = dcr_v29_0 > PORT PLB_dcrClk = PLB_TO_DCR_CLK <------------- new connection > PORT PLB_dcrRst = PLB_TO_DCR_RST <------------- new connection > END > > 3. I tried reading the memory directly from XMD and got "Debug memory > access check failed. Section, 0x87000200-0x8700203 not accessible from > processor debug interface. > I used 0x87000200 because DCR's offset is 128 (C_DCR_BASEADDR = > 0b0010000000) and to translate to PLB format, I multiplied by 4 as > suggested. However, I also tried other values including 0x87000080, > 0x87000100, 0x87000400, 0x87000800, 0x87001000, etc). Same result. > > It looks like the address is either not decodable or not accessible > due to misconnected ports. What do you think? Hello, I don't know where else I find find the answer to it, but I still cannot access the registers of a device sitting on DCR bus over plb to dcr bridge. How can I check whether the bridge is alive? (I don't have chipscope) None of the peripheral's dcr registers are accessible. My main suspicion is that the Rst and Clk pins are improperly connected. Someone must have used this before. I connected PORT PLB_dcrClk and PLB_dcrRst of the bridge to DCR_Clk and DCR_Rst of the peripheral. I am sure that I am doing the proper register translation (tried both, direct and multiplication by 4 as specified by the dcr spec). Thanks
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