Single Port Rom created by Core Generator configurable by generic values!!!!
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From: bellatoise on 1 Feb 2010 11:02 >On 1 =C5=9Eubat, 16:45, Enes Erdin <eneser...(a)gmail.com> wrote: >> On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...(a)gmail.com> wrote: >> >> >> >> > Hi, >> >> > My query is the next: >> > I'm working with Xilinx Ise Design Suite 11.1. >> > I need some ROMS with differents values of depth, width and initializat= >ion >> > files that I want to instantiate in one proyect. I need a generic ROM, = >so I >> > created one with Core Generator and I got its HDL code =C2=A0using View= > HDL >> > functional Model. >> > Then I introduced the values of width, depth and initialization file li= >ke >> > generics values. In the proyect, I generated the ROMS intantiating this= > HDL >> > code, each one with differents values. >> >> > When I sintetize the proyect appears some warnings like those: >> > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not at= >tach >> > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. >> > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. >> > WARNING:Xst:616 - Invalid property "width 8": Did not attach to >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. >> >> > Is there another way to get a ROM with Core Generator so that it can be >> > instantiated in the proyect and form there I can generate differents RO= >Ms >> > since te core that I created with differents the values of width, depth= > and >> > =C2=A0 initialization file?? >> >> > Thank you >> >> > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0 >> > Posted throughhttp://www.FPGARelated.com >> >> Take a look at creating ROMs using textio operations, that is, create >> your own ROM via VHDL. I hope it will solve your problem. >> >> --enes > >> via VHDL > >make that HDL > Ok, I can do my own ROM via HDL but I need to use a CORE. What can I do?? I have to use a Core for demands of the proyect. Thank you --------------------------------------- Posted through http://www.FPGARelated.com
From: RCIngham on 1 Feb 2010 12:26
> >Ok, I can do my own ROM via HDL but I need to use a CORE. What can I do?? >I have to use a Core for demands of the proyect. >Thank you > It's very difficult to 'genericise' the CoreGen outputs, although certainly possible for some types of cores. You could have a 'generic wrapper' that calls up different CoreGen outputs, for instance in VHDL using conditional generate statements (assuming that the company coding standards let you). Or you could just take the pain... --------------------------------------- Posted through http://www.FPGARelated.com |