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From: Mawa_fugo on 9 Apr 2010 10:05
Our PCB guy saying there's no enough room for Vccint pins (all
converge at center of the chip) so that each pin has one 0.01 uF
decoupling cap. As a result we have just 12 caps for 23 vccint
pins !!!

Wonder if anyone out there has similar pcb placement problem like us,
and how you solve it ?


TIA

From: Mawa_fugo on 9 Apr 2010 10:26
On Apr 9, 9:05 am, Mawa_fugo <cco...(a)netscape.net> wrote:
> Our PCB guy saying there's no enough room for Vccint pins (all
> converge at center of the chip) so that each pin has one 0.01 uF
> decoupling cap.  As a result we have just 12 caps for 23 vccint
> pins !!!
>
> Wonder if anyone out there has similar pcb placement problem like us,
> and how you solve it ?
>
> TIA

btw, those caps are in 402 package,
From: Symon on 9 Apr 2010 10:59
On 4/9/2010 3:26 PM, Mawa_fugo wrote:
> On Apr 9, 9:05 am, Mawa_fugo<cco...(a)netscape.net> wrote:
>> Our PCB guy saying there's no enough room for Vccint pins (all
>> converge at center of the chip) so that each pin has one 0.01 uF
>> decoupling cap. As a result we have just 12 caps for 23 vccint
>> pins !!!
>>
>> Wonder if anyone out there has similar pcb placement problem like us,
>> and how you solve it ?
>>
>> TIA
>
> btw, those caps are in 402 package,

Fit them on the backside from the FPGA. Use round pads on the 0402 caps
so they fit in between the via array.

Better still, ignore Xilinx's ridiculously conservative recommendations
and design it properly.

http://www.x2y.com/bypass/mount/backside_cap.pdf

HTH, Syms.


From: John Adair on 9 Apr 2010 11:23
It's basically impossible to do on a cost effective board. In practise
you can get away with a lot less of them if you planes are done well
and paired properly with a ground plane. Array capacitors we also use
a lot for density and you can see those on all of our development
boards for Spartan-3 etc.

John Adair
Enterpoint Ltd.


On 9 Apr, 15:05, Mawa_fugo <cco...(a)netscape.net> wrote:
> Our PCB guy saying there's no enough room for Vccint pins (all
> converge at center of the chip) so that each pin has one 0.01 uF
> decoupling cap.  As a result we have just 12 caps for 23 vccint
> pins !!!
>
> Wonder if anyone out there has similar pcb placement problem like us,
> and how you solve it ?
>
> TIA

From: Mawa_fugo on 9 Apr 2010 12:04
On Apr 9, 10:23 am, John Adair <g...(a)enterpoint.co.uk> wrote:
> It's basically impossible to do on a cost effective board. In practise
> you can get away with a lot less of them if you planes are done well
> and paired properly with a ground plane. Array capacitors we also use
> a lot for density and you can see those on all of our development
> boards for Spartan-3 etc.
>
> John Adair
> Enterpoint Ltd.
>
> On 9 Apr, 15:05, Mawa_fugo <cco...(a)netscape.net> wrote:
>
> > Our PCB guy saying there's no enough room for Vccint pins (all
> > converge at center of the chip) so that each pin has one 0.01 uF
> > decoupling cap.  As a result we have just 12 caps for 23 vccint
> > pins !!!
>
> > Wonder if anyone out there has similar pcb placement problem like us,
> > and how you solve it ?
>
> > TIA
>
>

I found this ug454, about the development board using the same part

http://www.xilinx.com/support/documentation/boards_and_kits/ug454_sp3a_dsp_start_ug.pdf

Page 56 they're talking about the ladder caps for Vccint 1.2V,
there're 13 caps of 0.01 and several other values, makes up total of
25 caps. There's no footprint image for them !!

I guess, just the 13 high speed caps are placed on the back of the
chip, right at the via - impossible to place bigger caps in that area

Wonder if someone has the image of the bottom of this board ?

TIA





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