I'd rather switch than fight!
in [FPGA]
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From: rickman on 9 Apr 2010 10:07 I think I have about had it with VHDL. I've been using the numeric_std library and eventually learned how to get around the issues created by strong typing although it can be very arcane at times. I have read about a few suggestions people are making to help with some aspects of the language, like a selection operator like Verilog has. But it just seems like I am always fighting some aspect of the VHDL language. I guess part of my frustration is that I have yet to see where strong typing has made a real difference in my work... at least an improvement. My customer uses Verilog and has mentioned several times how he had tried using VHDL and found it too arcane to bother with. He works on a much more practical level than I often do and it seems to work well for him. One of my goals over the summer is to teach myself Verilog so that I can use it as well as I currently use VHDL. Then I can make a fully informed decision about which I will continue to use. I'd appreciate pointers on good references, web or printed. Without starting a major argument, anyone care to share their feelings on the differences in the two languages? Rick
From: Andy on 9 Apr 2010 10:50 Before the fixed and floating point packages came out, I would have said there is little difference regarding RTL capabilities between Verilog and VHDL. But those two packages revealed a fundamental strength of VHDL that simply does not exist in verilog. By simply writing a new package, a whole new capability was created that would take a substantial language change in Verilog. Yes, the as-released packages took advantage of features only available in a related change in the language itself, but the "compatibility" packages ably demonstrate that the working concept is viable even within the confines the original language, thus demonstrating the true strengh of the basic language of VHDL. Not that the fixed/floating point packages are nirvana, but they do represent a huge step in the right direction. If we only had assignment operator overloading in VHDL, it would be much closer... Still, that's a capability much closer to reality in VHDL than in Verilog. Sure, verilog has many "built-in" tricks, but they are only applicable to the existing type structure, and cannot be expanded upon without revising the language itself. Even before the fixed/floating point packages, integers simply work in VHDL (within the range limitations), whereas in Verilog, they don't always, but they also don't complain when they don't work either. In general, strong typing and built-in bounds checking in VHDL catch more problems, closer to the source of the problems, with no additional code being written, than is possible in Verilog without having to write A LOT of extra code. It seems for almost every weak- typing-enabled shortcut in verilog, there is also a hidden, often silent, "gotcha" to go along with it. Andy
From: Patrick Maupin on 9 Apr 2010 12:53 On Apr 9, 9:07 am, rickman <gnu...(a)gmail.com> wrote: > I think I have about had it with VHDL. I've been using the > numeric_std library and eventually learned how to get around the > issues created by strong typing although it can be very arcane at > times. I have read about a few suggestions people are making to help > with some aspects of the language, like a selection operator like > Verilog has. But it just seems like I am always fighting some aspect > of the VHDL language. > > I guess part of my frustration is that I have yet to see where strong > typing has made a real difference in my work... at least an > improvement. My customer uses Verilog and has mentioned several times > how he had tried using VHDL and found it too arcane to bother with. > He works on a much more practical level than I often do and it seems > to work well for him. > > One of my goals over the summer is to teach myself Verilog so that I > can use it as well as I currently use VHDL. Then I can make a fully > informed decision about which I will continue to use. I'd appreciate > pointers on good references, web or printed. > > Without starting a major argument, anyone care to share their feelings > on the differences in the two languages? > > Rick The best online references are the Sutherland Verilog references. There is an online HTML reference for Verilog 95 (excellent), and a PDF for Verilog 2001 (good): http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html http://sutherland-hdl.com/online_verilog_ref_guide/verilog_2001_ref_guide.pdf Cliff Cummings has a lot of good papers on Verilog at his site: http://sunburst-design.com/papers/ In particular, if you read and carefully grok his paper about non- blocking vs. blocking assignments, you will be well on your way to being a Verilog wizard: http://sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf Regards, Pat
From: gabor on 9 Apr 2010 14:25 On Apr 9, 10:07 am, rickman <gnu...(a)gmail.com> wrote: > I think I have about had it with VHDL. I've been using the > numeric_std library and eventually learned how to get around the > issues created by strong typing although it can be very arcane at > times. I have read about a few suggestions people are making to help > with some aspects of the language, like a selection operator like > Verilog has. But it just seems like I am always fighting some aspect > of the VHDL language. > > I guess part of my frustration is that I have yet to see where strong > typing has made a real difference in my work... at least an > improvement. My customer uses Verilog and has mentioned several times > how he had tried using VHDL and found it too arcane to bother with. > He works on a much more practical level than I often do and it seems > to work well for him. > > One of my goals over the summer is to teach myself Verilog so that I > can use it as well as I currently use VHDL. Then I can make a fully > informed decision about which I will continue to use. I'd appreciate > pointers on good references, web or printed. > > Without starting a major argument, anyone care to share their feelings > on the differences in the two languages? > > Rick At the end of the day, it really comes down to how you can be more productive. If you tend to code with many levels of abstraction you may do better with VHDL. I find that I am more productive with Verilog, but it could be because I tend to look at hardware at a fairly detailed level, a bottom-up approach if you will. I inherited Verilog projects at my current place of employment and just stuck with the language as it grew on me. At one point I read Thomas & Moorby's green book from cover to cover. However it described Verilog 95, not the more commonly used Verilog 2001, and was not a particularly good reference book. I keep a copy of the Doulos Golden Reference handy for the bits I don't use every day. Good Luck, Gabor
From: glen herrmannsfeldt on 9 Apr 2010 15:01
In comp.arch.fpga rickman <gnuarm(a)gmail.com> wrote: (snip) > Without starting a major argument, anyone care to share their feelings > on the differences in the two languages? I started with verilog, as that is what others I was working with were doing, and was also told that it was a better choice for previous C programmers. (Not that I believe that HDL should be related to a software language.) At some point, I learned to read VHDL, at least enough to convert an module to verilog when needed, or to understand why something didn't work the way I thought it should. (I had one project with schematic capture, VHDL, and AHDL, and then I started adding verilog to it.) It seems to me that verilog, similar to C, gets the ideas across without being excessively wordy. In comparison to some other languages, I find the convenience in C of converting between char and int without the need for any special conversion operation (such as the Fortran CHAR function) convenient. Well, I write my verilog mostly using continuous assignment, with a fairly small amount of behavioral verilog. For those who prefer behavioral coding, the recommendation might be different. -- glen |