From: LC on
Hello,

While using Qurtus II with a design that has only
one section where timing is critical I got on the classical timing
analyzer the relevant warnings about what it finds and that is
absolutely fine and as expected.

However on the remaining part of the design, (some quasi static
configurations etc) that runs very slowly and have its signals
driven by software with an external microcontroller, I have hundreds of
warnings of things that might not operate as expected and fail for all
sorts of reasons, this is related with stupid sequences behaviours and
operations that will never happen as this is a software controlled
thing, and those operations are well defined and do work obviously as
expected while properly commanded by software.
Surely I don't blame the timing analyzer to check those... of course...
but...

Question:

How can I instruct quartus II to do not perform those timing checks for
a number of selected paths/signals ?

This is annoying and unnecessary time consumption and a major
distraction to the real things I'm worried and try to get working well
on this design.

Any help ?

Thanks.


Luis C.
From: jt_eaton on
>Hello,
>
>Question:
>
>How can I instruct quartus II to do not perform those timing checks for
>a number of selected paths/signals ?
>
>This is annoying and unnecessary time consumption and a major
>distraction to the real things I'm worried and try to get working well
>on this design.
>
>Any help ?
>
>Thanks.
>
>
>Luis C.
>
check out AN481 Applying Multicycle exceptions in the TimeQuest timing
analyzer

---------------------------------------
Posted through http://www.FPGARelated.com
From: Muzaffer Kal on
On Tue, 04 May 2010 11:50:10 +0100, LC <cupidoREMOVE(a)mail.ua.pt>
wrote:

>Hello,
>
>While using Qurtus II with a design that has only
>one section where timing is critical I got on the classical timing
>analyzer the relevant warnings about what it finds and that is
>absolutely fine and as expected.
>
>However on the remaining part of the design, (some quasi static
>configurations etc) that runs very slowly and have its signals
>driven by software with an external microcontroller, I have hundreds of
>warnings of things that might not operate as expected and fail for all
>sorts of reasons, this is related with stupid sequences behaviours and
>operations that will never happen as this is a software controlled
>thing, and those operations are well defined and do work obviously as
>expected while properly commanded by software.
>Surely I don't blame the timing analyzer to check those... of course...
>but...
>
>Question:
>
>How can I instruct quartus II to do not perform those timing checks for
>a number of selected paths/signals ?
>
>This is annoying and unnecessary time consumption and a major
>distraction to the real things I'm worried and try to get working well
>on this design.
>
>Any help ?

You can use set_false_path or a command like set_case_analysis. But
the latter is for things which really don't change during functional
mode (ie you need a reset after changing the value etc.) and the
former can be really dangerous; even if it's constant for long periods
of time, it needs to change at some point and there maybe functional
issues at that point of change. You need to guarantee that your design
will not go into an unrecoverable mode when you change one of these
configuration bits.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
From: LC on
Thanks.

LC