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From: Antti on 22 Sep 2009 07:18 signal next : integer range -1 to 2; function find_first(vector, enable : std_ulogic_vector(0 to 2)) return integer is variable result : integer; begin result := -1; -- omitted calc of first in range of 0..2 return result; end find_first; next <= find_first(valid, enable); ------- is this code fully synthesis safe? how many bits is variable next? this is not my code, i need to troubleshoot it, i guess it is 100% legal code, just curious how are synthesis tools doing it next could be 2 bits, but then -1 would map to 0 ? or ? Antti
From: glen herrmannsfeldt on 22 Sep 2009 07:53 Antti <antti.lukats(a)googlemail.com> wrote: < signal next : integer range -1 to 2; < function find_first(vector, enable : std_ulogic_vector(0 to 2)) < return integer is < variable result : integer; < begin < result := -1; < -- omitted calc of first in range of 0..2 < return result; < end find_first; < next <= find_first(valid, enable); < is this code fully synthesis safe? < how many bits is variable next? I have done priority encoders in verilog before, though always specifying the width of the result. < this is not my code, i need to troubleshoot it, < i guess it is 100% legal code, just curious how are < synthesis tools doing it I believe it is fine. In verilog, the result would be 32 bits (on the usual implementation). If you assign the result to a something smaller, it will truncate. Also, the tools are pretty good at removing unused logic. Still, I don't see any reason not to specify the size of the result. < next could be 2 bits, but then -1 would map to 0 ? < or ? 3 (the low two bits of twos complement -1) -- glen
From: Antti.Lukats on 22 Sep 2009 08:10 On Sep 22, 2:53 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > Antti <antti.luk...(a)googlemail.com> wrote: > > < signal next : integer range -1 to 2; > > < function find_first(vector, enable : std_ulogic_vector(0 to 2)) > < return integer is > < variable result : integer; > < begin > < result := -1; > < -- omitted calc of first in range of 0..2 > < return result; > < end find_first; > > < next <= find_first(valid, enable); > > < is this code fully synthesis safe? > < how many bits is variable next? > > I have done priority encoders in verilog before, though > always specifying the width of the result. > > < this is not my code, i need to troubleshoot it, > < i guess it is 100% legal code, just curious how are > < synthesis tools doing it > > I believe it is fine. In verilog, the result would be 32 bits > (on the usual implementation). If you assign the result to a > something smaller, it will truncate. Also, the tools are pretty > good at removing unused logic. Still, I don't see any reason > not to specify the size of the result. > > < next could be 2 bits, but then -1 would map to 0 ? > < or ? > > 3 (the low two bits of twos complement -1) > > -- glen yeah i assumed 3 but it could be 2 if doing hand coded functionally same code Antti
From: KJ on 22 Sep 2009 08:20 On Sep 22, 7:18 am, Antti <antti.luk...(a)googlemail.com> wrote: > signal next : integer range -1 to 2; > > function find_first(vector, enable : std_ulogic_vector(0 to 2)) > return integer is > variable result : integer; > begin > result := -1; > -- omitted calc of first in range of 0..2 > return result; > end find_first; > > next <= find_first(valid, enable); > > ------- > is this code fully synthesis safe? It looks to be. > how many bits is variable next? > To know that you would need to look at the declaration for 'next' not the function that assigns to 'next'. The defined range for the integer will end up defining the number of bits required for synthesis. Whether it can be implemented in less bits would depend on whether or not the logic reduces to something smaller. For example, the code you listed 'as is' would reduce to a constant and therefore most likely result in 0 bits for 'next'. signal next: integer; -- 32 bits signal next: integer range 0 to 7; -- 3 bits signal next: integer range -3 to 3; -- 3 bits signal next: integer range -4 to 3; -- 3 bits also > > next could be 2 bits, but then -1 would map to 0 ? > or ? -1 in two bits is "11" Kevin Jennings
From: KJ on 22 Sep 2009 08:27
On Sep 22, 7:18 am, Antti <antti.luk...(a)googlemail.com> wrote: > signal next : integer range -1 to 2; > I missed this line in my first post. So for starters, 'next' would have to be 3 bits based on the defined range. As I mentioned in the previous post, depending on what the logic actually is, some of the bits could be optomized away during synthesis. If there is a two bit (or one bit) implementation, synthesis tools will most likely find it. Reduction of simple boolean logic as in this case is their strong suit. Kevin Jennings |