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From: Rob Gaddi on 12 Mar 2010 12:29
Hey y'all --

Lately my company's been poking around at our overall design flow,
trying to work out how to make things happen in better, more logical
fashions. And one of the things that comes to mind is the pinning of
FPGAs, i.e. determining which signal's going to go where.
Traditionally around here, we've allowed the pinning to be pretty much
at the PCB layout engineer's discretion with only minimal input from
me, i.e. this has to go to a GCLK, these all need to be on the same I/O
bank for voltage reasons.

I was just wondering how everyone else fits actually bringing the
signals out into the design cycle? Do you do the FPGA first, then let
the placement tools pick your layout for you? Some kind of iterative
process?

Anyone with thoughts, feel free to share.

Thanks,
Rob

--
Rob Gaddi, Highland Technology
Email address is currently out of order
From: John_H on 12 Mar 2010 13:15
On Mar 12, 12:29 pm, Rob Gaddi <rga...(a)technologyhighland.com> wrote:
> Hey y'all --
>
> Lately my company's been poking around at our overall design flow,
> trying to work out how to make things happen in better, more logical
> fashions.  And one of the things that comes to mind is the pinning of
> FPGAs, i.e. determining which signal's going to go where.
> Traditionally around here, we've allowed the pinning to be pretty much
> at the PCB layout engineer's discretion with only minimal input from
> me, i.e. this has to go to a GCLK, these all need to be on the same I/O
> bank for voltage reasons.
>
> I was just wondering how everyone else fits actually bringing the
> signals out into the design cycle?  Do you do the FPGA first, then let
> the placement tools pick your layout for you?  Some kind of iterative
> process?
>
> Anyone with thoughts, feel free to share.
>
> Thanks,
> Rob
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

Often it's too difficult to fully specify the FPGA such that pins are
defined clearly what can be used and what can't.

The normal design flow I've encountered is working iteratively with
the layout designer. When a placement is determined, the nort/south/
east/west orientation is pretty reasonable to figure out what signals
should be in which banks. The FPGA designer produces an initial pin
placement without necessarily having a full design to back it up,
based on what would work well from a routability standpoint. When
"passed off" to the layout person, it's usually underscored what pins
are tied to a bank (VCCIO issues) and which pins are absolute (GCLK,
DDR interface).

I've spent a couple days getting things manually pinned out so the
layout should be clean: fewer vias, good escapes, decent signal
integrity.

Having a preference for surface signals versus buried signals, it's
easy to define the outer two rows for top layer routing and rows
further in for internal or back side signals.

The more pins, the more trouble it is, perhaps, but the cleaner the
interaction with the FPGA tool flow (UCF file ready early) and board
layout.
From: Symon on 12 Mar 2010 13:32
On 3/12/2010 5:29 PM, Rob Gaddi wrote:

> Traditionally around here, we've allowed the pinning to be pretty much
> at the PCB layout engineer's discretion with only minimal input from
> me, i.e. this has to go to a GCLK, these all need to be on the same I/O
> bank for voltage reasons.
>
Rob,
I do the same. The PCB routing is generally more restricted than the
routing on the FPGA. With sub ns rise times, the PCB routing is very
important.
Cheers, Syms.
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