From: Rick Jones on
"Andy \"Krazy\" Glew" <ag-news(a)patten-glew.net> wrote:
> (One of the big disappointments of my life is that it is not typical
> for programmers to work in isolated places, like on top of
> volcanoes.)

Hmm, that doesn't sound prudent. Forget eruptions - when you don't
make schedule it is that much easier for "them" to toss you into the
caldera.

rick jones
--
Process shall set you free from the need for rational thought.
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...
From: Rick Jones on
"Andy \"Krazy\" Glew" <ag-news(a)patten-glew.net> wrote:
> Yesterday I met with Ivan Sutherland at Portland State University.

> Amongst other things, Ivan pitched his capacitatively coupled
> interconnect between chips.

Perhaps I'm about to have a lesson in the six degrees of separation,
but isn't that the thing Sun was touting several years ago?

rick jones
--
No need to believe in either side, or any side. There is no cause.
There's only yourself. The belief is in your own precision. - Joubert
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...
From: MitchAlsup on
On Mar 3, 3:24 pm, Rick Jones <rick.jon...(a)hp.com> wrote:
> "Andy \"Krazy\" Glew" <ag-n...(a)patten-glew.net> wrote:
>
> > Yesterday I met with Ivan Sutherland at Portland State University.
> > Amongst other things, Ivan pitched his capacitatively coupled
> > interconnect between chips.
>
> Perhaps I'm about to have a lesson in the six degrees of separation,
> but isn't that the thing Sun was touting several years ago?

Yes, or at least a cousin.

Mitch
From: Terje Mathisen "terje.mathisen at on
MitchAlsup wrote:
> I intend that the ECS be used as a 'paging' area. That is the memory
> is not accessible by a load or a store, but is addressible as if the
> ECS were a disk with zero rotational latency, and performs transfers
> in page sized units with about the delay of a cache line transfer of
> current era. Done this way, the size of the coherent domain is samll
> enough that coherence checking does not increase memory access time,
> but large memory is accessible because the paging is so fast. Much of
> the other detail is to make the memory management updates as fast as
> the data transfers.

Very interesting...

[snip]

> One big reason to punt the I/O to ECS is that you really don't want I/
> O requests from the 1024-4096 SATA disks in a system of the
> aforementioned scale to swamp the memory interconnect on the coherent
> side of things. It is expected that only a moderate portion of the
> total available BW into the ECS is used by the computation amalgam,
> leaving a significant amount of BW to the I/O devices.

This part I agree totally with, I would really prefer to be able to
limit coherence traffic to a tiny subset of the total memory available
to each cpu/core.

Sounds like a very good match for MPI-style programming.

>
> There are a "few" software issue to resolve also.

You think so?

Isn't that just a SMOP?

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
From: "Andy "Krazy" Glew" on
Rick Jones wrote:
> "Andy \"Krazy\" Glew" <ag-news(a)patten-glew.net> wrote:
>> Yesterday I met with Ivan Sutherland at Portland State University.
>
>> Amongst other things, Ivan pitched his capacitatively coupled
>> interconnect between chips.
>
> Perhaps I'm about to have a lesson in the six degrees of separation,
> but isn't that the thing Sun was touting several years ago?
>
> rick jones

0 degrees of separation.

Ivan Sutherland was the guy doing this at Sun Research. Actually, Ivan started Sun Research.