Xilinx FFT core -- Is varying precision through the core possible?
in [FPGA]
|
From: onkars on 6 May 2010 13:22 Hi, Can I set the XIlinx FFT core such that the early (maybe first 5 out of 10) stages use smaller precision bits (same as input precision) --- and they use scaling. But the later 5 stages don't use scaling --- instead we allow them more precision bits. This will help me to use less precision (and hence less hardware) with scaling wherever possible. (using the small precision throughout the FFT gives underflow results) With initial stages scaled and later stages allowed bit growth --- I can prevent overflow as well as achieve the meaningful results (with higher precision output) while saving hardware (since only later stages use high precision) Does this make sense? Is this possible with Xilinx FFT core? Onkar --------------------------------------- Posted through http://www.FPGARelated.com
From: onkars on 6 May 2010 19:49 Any help will be really appreciated. > >Hi, > > >Can I set the XIlinx FFT core such that the early (maybe first 5 out of 10) >stages use smaller precision bits (same as input precision) --- and they >use scaling. But the later 5 stages don't use scaling --- instead we allow >them more precision bits. > >This will help me to use less precision (and hence less hardware) with >scaling wherever possible. (using the small precision throughout the FFT >gives underflow results) With initial stages scaled and later stages >allowed bit growth --- I can prevent overflow as well as achieve the >meaningful results (with higher precision output) while saving hardware >(since only later stages use high precision) > >Does this make sense? Is this possible with Xilinx FFT core? > > >Onkar > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.com
|
Pages: 1 Prev: FPGA Compilation Time Windows vs Linux Next: Site for some reason, and forbidden |