Prev: Problems simulation plb_gemac core for Virtex-II Pro
Next: Spartan 3E starter kit DDR SDRAM code
From: MM on 4 Jul 2006 00:45
Gary,

h doesn't have a source in your code. You need to add something like this:
h <= slv_reg0;
Or just use slv_reg0 instead of h as input to your inverter and in the read
process.

/Mikhail



From: gary on 5 Jul 2006 21:07
>Gary,
>
>h doesn't have a source in your code. You need to add something like
this:
>h <= slv_reg0;
>Or just use slv_reg0 instead of h as input to your inverter and in the
read
>process.
>
>/Mikhail
>hey,
In user_ip.vhd file i used the following instantation in user logic
implementation
h<=slv_reg0;
k<=slv_reg1;
again synthesis is going on well but the same errors what i posted in my
first message are coming again.

And in the second method i disabled h & k signals directly i assigned
portmap(slv_reg0,slv_reg1) in following way
------------
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;

---attribute box_type : string;
--attribute box_type of inverter : component is "black_box";

begin

we: inverter
port map(slv_reg0,slv_reg1);
----------------------------
while synthesis following errors are generated....

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg1<9>>
Sources are:
Output signal of OBUF instance <we/t_9_OBUF>
Output signal of FDRE instance <slv_reg1_9>

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
<slv_reg1<13>>
Sources are:
Output signal of OBUF instance <we/t_13_OBUF>
Output signal of FDRE instance <slv_reg1_13>

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
<slv_reg1<21>>
Sources are:
Output signal of OBUF instance <we/t_21_OBUF>
Output signal of FDRE instance <slv_reg1_21>

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
<slv_reg1<27>>
Sources are:
Output signal of OBUF instance <we/t_27_OBUF>
Output signal of FDRE instance <slv_reg1_27>
----------------for all 0 to 31----------------------------
/gary





From: MM on 5 Jul 2006 23:55
Gary,

It seems you are thinking as if you were writing software. VHDL is a
hardware description language. You need to understand what hardware you are
trying to create. You have a separate write and read processes, which
essentially describe behaviour of a bunch (because you have more than a
single bit) of D flip-flops. The write process describes what is applied to
the D input and the read process what happens to the Q output. Thus, when
you see slv_reg in the write process on the left side of the assignment it
represents the D-input of the flip-flop, while when you see it on the right
side in the read process it represents the Q output of the same flip-flop,
i.e. stored content of the register.

/Mikhail







"gary" <rgarik(a)yahoo.com> wrote in message
news:3LWdnRqUwL34_zHZnZ2dneKdnZydnZ2d(a)giganews.com...
> >Gary,
> >
> >h doesn't have a source in your code. You need to add something like
> this:
> >h <= slv_reg0;
> >Or just use slv_reg0 instead of h as input to your inverter and in the
> read
> >process.
> >
> >/Mikhail
> >hey,
> In user_ip.vhd file i used the following instantation in user logic
> implementation
> h<=slv_reg0;
> k<=slv_reg1;
> again synthesis is going on well but the same errors what i posted in my
> first message are coming again.
>
> And in the second method i disabled h & k signals directly i assigned
> portmap(slv_reg0,slv_reg1) in following way
> ------------
> component inverter
> port( s : in std_logic_vector(0 to 31);
> t : out std_logic_vector(0 to 31));
> end component;
>
> ---attribute box_type : string;
> --attribute box_type of inverter : component is "black_box";
>
> begin
>
> we: inverter
> port map(slv_reg0,slv_reg1);
> ----------------------------
> while synthesis following errors are generated....
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg1<9>>
> Sources are:
> Output signal of OBUF instance <we/t_9_OBUF>
> Output signal of FDRE instance <slv_reg1_9>
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg1<13>>
> Sources are:
> Output signal of OBUF instance <we/t_13_OBUF>
> Output signal of FDRE instance <slv_reg1_13>
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg1<21>>
> Sources are:
> Output signal of OBUF instance <we/t_21_OBUF>
> Output signal of FDRE instance <slv_reg1_21>
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg1<27>>
> Sources are:
> Output signal of OBUF instance <we/t_27_OBUF>
> Output signal of FDRE instance <slv_reg1_27>
> ----------------for all 0 to 31----------------------------
> /gary
>
>
>
>
>


From: gary on 8 Jul 2006 19:02
>Gary,
>
>It seems you are thinking as if you were writing software. VHDL is a
>hardware description language. You need to understand what hardware you
are
>trying to create. You have a separate write and read processes, which
>essentially describe behaviour of a bunch (because you have more than a
>single bit) of D flip-flops. The write process describes what is applied
to
>the D input and the read process what happens to the Q output. Thus,
when
>you see slv_reg in the write process on the left side of the assignment
it
>represents the D-input of the flip-flop, while when you see it on the
right
>side in the read process it represents the Q output of the same
flip-flop,
>i.e. stored content of the register.
>
>/Mikhail
>
>
>
>
>
>
>
>"gary" <rgarik(a)yahoo.com> wrote in message
>news:3LWdnRqUwL34_zHZnZ2dneKdnZydnZ2d(a)giganews.com...
>> >Gary,
>> >
>> >h doesn't have a source in your code. You need to add something like
>> this:
>> >h <= slv_reg0;
>> >Or just use slv_reg0 instead of h as input to your inverter and in
the
>> read
>> >process.
>> >
>> >/Mikhail
>> >hey,
>> In user_ip.vhd file i used the following instantation in user
logic
>> implementation
>> h<=slv_reg0;
>> k<=slv_reg1;
>> again synthesis is going on well but the same errors what i posted in
my
>> first message are coming again.
>>
>> And in the second method i disabled h & k signals directly i assigned
>> portmap(slv_reg0,slv_reg1) in following way
>> ------------
>> component inverter
>> port( s : in std_logic_vector(0 to 31);
>> t : out std_logic_vector(0 to 31));
>> end component;
>>
>> ---attribute box_type : string;
>> --attribute box_type of inverter : component is "black_box";
>>
>> begin
>>
>> we: inverter
>> port map(slv_reg0,slv_reg1);
>> ----------------------------
>> while synthesis following errors are generated....
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
<slv_reg1<9>>
>> Sources are:
>> Output signal of OBUF instance <we/t_9_OBUF>
>> Output signal of FDRE instance <slv_reg1_9>
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg1<13>>
>> Sources are:
>> Output signal of OBUF instance <we/t_13_OBUF>
>> Output signal of FDRE instance <slv_reg1_13>
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg1<21>>
>> Sources are:
>> Output signal of OBUF instance <we/t_21_OBUF>
>> Output signal of FDRE instance <slv_reg1_21>
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg1<27>>
>> Sources are:
>> Output signal of OBUF instance <we/t_27_OBUF>
>> Output signal of FDRE instance <slv_reg1_27>
>> ----------------for all 0 to 31----------------------------
>> /gary
>>
>>hi mikhael,
sorry iam a beginner, thanks for ur information.In my
user_ip.vhd there are 2 process one for read & another for write, now i
want to access my inverter i.e one i/p & one o/p. so i have to write like
this (h<=slv_reg0;) in write process and (k<=slv_reg1;)in read process
because iam intended to connect the h to my i/p(s) of inverter and k to
o/p(t) of my inverter.
Can u tell me is this right?

If this is right when i synthesized my code like this following warning
msg is appearing:
WARNING:Xst:646 - Signal <k> is assigned but never used.
And while implementing same errors as before are appearing.


Before in my user_ip.vhd i used to write my logic (inverter) and when i
used to download it on my board and see it on the hyper terminal it works
fine. But when the same logic is added like a (ip core)i.e component
instantiation, i stucked at the above problems.

So can you guide me in this task.

thanks
gary

>>
>>
>>
>
>
>


From: MM on 10 Jul 2006 11:59
"gary" <rgarik(a)yahoo.com> wrote in message
news:lcidnVZfNa0MpC3ZRVn_vA(a)giganews.com...
> In my
> user_ip.vhd there are 2 process one for read & another for write, now i
> want to access my inverter i.e one i/p & one o/p. so i have to write like
> this (h<=slv_reg0;) in write process and (k<=slv_reg1;)in read process
> because iam intended to connect the h to my i/p(s) of inverter and k to
> o/p(t) of my inverter.
> Can u tell me is this right?

No, it's not. See below corrected write and read processes and assignement
for h.

======================================================
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_select is
when "100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

h <= slv_reg0;

-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select,h,k) is
begin

case slv_reg_read_select is
when "100" => slv_ip2bus_data <= h;
when "010" => slv_ip2bus_data <= k;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

======================================================

/Mikhail


First  |  Prev  |  Next  |  Last
Pages: 1 2 3
Prev: Problems simulation plb_gemac core for Virtex-II Pro
Next: Spartan 3E starter kit DDR SDRAM code